mirror of
https://github.com/c64scene-ar/llvm-6502.git
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AVX-512: Simplified MOV patterns, no functional changes.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@230954 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Elena Demikhovsky
parent
66c89ee492
commit
e206743835
@ -74,6 +74,15 @@ class X86VectorVTInfo<int numelts, ValueType eltvt, RegisterClass rc,
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!if (!eq (Size, 128), "v2i64",
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!if (!eq (Size, 256), "v4i64",
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VTName)), VTName));
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PatFrag AlignedLdFrag = !cast<PatFrag>("alignedload" #
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!if (!eq (TypeVariantName, "i"),
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!if (!eq (Size, 128), "v2i64",
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!if (!eq (Size, 256), "v4i64",
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!if (!eq (Size, 512),
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!if (!eq (EltSize, 64), "v8i64", "v16i32"),
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VTName))), VTName));
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PatFrag ScalarLdFrag = !cast<PatFrag>("load" # EltVT);
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// The corresponding float type, e.g. v16f32 for v16i32
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@ -2071,173 +2080,160 @@ def : Pat<(v8i1 (X86vsrli VK8:$src, (i8 imm:$imm))),
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// AVX-512 - Aligned and unaligned load and store
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//
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multiclass avx512_load<bits<8> opc, string OpcodeStr, PatFrag ld_frag,
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RegisterClass KRC, RegisterClass RC,
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ValueType vt, ValueType zvt, X86MemOperand memop,
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Domain d, bit IsReMaterializable = 1> {
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let hasSideEffects = 0 in {
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def rr : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins RC:$src),
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multiclass avx512_load<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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PatFrag ld_frag, bit IsReMaterializable = 1> {
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let hasSideEffects = 0 in {
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def rr : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst), (ins _.RC:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [],
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d>, EVEX;
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def rrkz : AVX512PI<opc, MRMSrcReg, (outs RC:$dst), (ins KRC:$mask, RC:$src),
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_.ExeDomain>, EVEX;
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def rrkz : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
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(ins _.KRCWM:$mask, _.RC:$src),
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!strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
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"${dst} {${mask}} {z}, $src}"), [], d>, EVEX, EVEX_KZ;
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}
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"${dst} {${mask}} {z}, $src}"), [], _.ExeDomain>,
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EVEX, EVEX_KZ;
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let canFoldAsLoad = 1, isReMaterializable = IsReMaterializable,
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SchedRW = [WriteLoad] in
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def rm : AVX512PI<opc, MRMSrcMem, (outs RC:$dst), (ins memop:$src),
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def rm : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst), (ins _.MemOp:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(set RC:$dst, (vt (bitconvert (ld_frag addr:$src))))],
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d>, EVEX;
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[(set _.RC:$dst, (_.VT (bitconvert (ld_frag addr:$src))))],
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_.ExeDomain>, EVEX;
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let AddedComplexity = 20 in {
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let Constraints = "$src0 = $dst", hasSideEffects = 0 in {
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let hasSideEffects = 0 in
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def rrk : AVX512PI<opc, MRMSrcReg, (outs RC:$dst),
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(ins RC:$src0, KRC:$mask, RC:$src1),
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!strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
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"${dst} {${mask}}, $src1}"),
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[(set RC:$dst, (vt (vselect KRC:$mask,
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(vt RC:$src1),
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(vt RC:$src0))))],
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d>, EVEX, EVEX_K;
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let Constraints = "$src0 = $dst" in {
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def rrk : AVX512PI<opc, MRMSrcReg, (outs _.RC:$dst),
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(ins _.RC:$src0, _.KRCWM:$mask, _.RC:$src1),
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!strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
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"${dst} {${mask}}, $src1}"),
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[(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
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(_.VT _.RC:$src1),
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(_.VT _.RC:$src0))))], _.ExeDomain>,
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EVEX, EVEX_K;
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let mayLoad = 1, SchedRW = [WriteLoad] in
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def rmk : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
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(ins RC:$src0, KRC:$mask, memop:$src1),
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def rmk : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
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(ins _.RC:$src0, _.KRCWM:$mask, _.MemOp:$src1),
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!strconcat(OpcodeStr, "\t{$src1, ${dst} {${mask}}|",
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"${dst} {${mask}}, $src1}"),
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[(set RC:$dst, (vt
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(vselect KRC:$mask,
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(vt (bitconvert (ld_frag addr:$src1))),
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(vt RC:$src0))))],
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d>, EVEX, EVEX_K;
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[(set _.RC:$dst, (_.VT
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(vselect _.KRCWM:$mask,
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(_.VT (bitconvert (ld_frag addr:$src1))),
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(_.VT _.RC:$src0))))], _.ExeDomain>, EVEX, EVEX_K;
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}
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let mayLoad = 1, SchedRW = [WriteLoad] in
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def rmkz : AVX512PI<opc, MRMSrcMem, (outs RC:$dst),
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(ins KRC:$mask, memop:$src),
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!strconcat(OpcodeStr, "\t{$src, ${dst} {${mask}} {z}|",
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"${dst} {${mask}} {z}, $src}"),
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[(set RC:$dst, (vt
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(vselect KRC:$mask,
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(vt (bitconvert (ld_frag addr:$src))),
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(vt (bitconvert (zvt immAllZerosV))))))],
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d>, EVEX, EVEX_KZ;
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def rmkz : AVX512PI<opc, MRMSrcMem, (outs _.RC:$dst),
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(ins _.KRCWM:$mask, _.MemOp:$src),
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OpcodeStr #"\t{$src, ${dst} {${mask}} {z}|"#
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"${dst} {${mask}} {z}, $src}",
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[(set _.RC:$dst, (_.VT (vselect _.KRCWM:$mask,
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(_.VT (bitconvert (ld_frag addr:$src))), _.ImmAllZerosV)))],
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_.ExeDomain>, EVEX, EVEX_KZ;
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}
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}
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multiclass avx512_load_vl<bits<8> opc, string OpcodeStr, string ld_pat,
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string elty, string elsz, string vsz512,
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string vsz256, string vsz128, Domain d,
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Predicate prd, bit IsReMaterializable = 1> {
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multiclass avx512_alignedload_vl<bits<8> opc, string OpcodeStr,
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AVX512VLVectorVTInfo _,
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Predicate prd,
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bit IsReMaterializable = 1> {
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let Predicates = [prd] in
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defm Z : avx512_load<opc, OpcodeStr,
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!cast<PatFrag>(ld_pat##"v"##vsz512##elty##elsz),
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!cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
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!cast<ValueType>("v"##vsz512##elty##elsz), v16i32,
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!cast<X86MemOperand>(elty##"512mem"), d,
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IsReMaterializable>, EVEX_V512;
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defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.AlignedLdFrag,
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IsReMaterializable>, EVEX_V512;
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let Predicates = [prd, HasVLX] in {
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defm Z256 : avx512_load<opc, OpcodeStr,
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!cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
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"v"##vsz256##elty##elsz, "v4i64")),
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!cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
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!cast<ValueType>("v"##vsz256##elty##elsz), v8i32,
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!cast<X86MemOperand>(elty##"256mem"), d,
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IsReMaterializable>, EVEX_V256;
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defm Z128 : avx512_load<opc, OpcodeStr,
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!cast<PatFrag>(ld_pat##!if(!eq(elty,"f"),
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"v"##vsz128##elty##elsz, "v2i64")),
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!cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
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!cast<ValueType>("v"##vsz128##elty##elsz), v4i32,
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!cast<X86MemOperand>(elty##"128mem"), d,
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IsReMaterializable>, EVEX_V128;
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defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.AlignedLdFrag,
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IsReMaterializable>, EVEX_V256;
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defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.AlignedLdFrag,
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IsReMaterializable>, EVEX_V128;
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}
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}
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multiclass avx512_load_vl<bits<8> opc, string OpcodeStr,
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AVX512VLVectorVTInfo _,
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Predicate prd,
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bit IsReMaterializable = 1> {
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let Predicates = [prd] in
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defm Z : avx512_load<opc, OpcodeStr, _.info512, _.info512.LdFrag,
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IsReMaterializable>, EVEX_V512;
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multiclass avx512_store<bits<8> opc, string OpcodeStr, PatFrag st_frag,
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ValueType OpVT, RegisterClass KRC, RegisterClass RC,
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X86MemOperand memop, Domain d> {
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let Predicates = [prd, HasVLX] in {
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defm Z256 : avx512_load<opc, OpcodeStr, _.info256, _.info256.LdFrag,
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IsReMaterializable>, EVEX_V256;
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defm Z128 : avx512_load<opc, OpcodeStr, _.info128, _.info128.LdFrag,
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IsReMaterializable>, EVEX_V128;
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}
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}
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multiclass avx512_store<bits<8> opc, string OpcodeStr, X86VectorVTInfo _,
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PatFrag st_frag> {
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let isCodeGenOnly = 1, ForceDisassemble = 1, hasSideEffects = 0 in {
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def rr_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst), (ins RC:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"), [], d>,
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EVEX;
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def rr_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst), (ins _.RC:$src),
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OpcodeStr # "\t{$src, $dst|$dst, $src}", [],
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_.ExeDomain>, EVEX;
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let Constraints = "$src1 = $dst" in
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def rrk_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
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(ins RC:$src1, KRC:$mask, RC:$src2),
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!strconcat(OpcodeStr,
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"\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}"), [], d>,
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EVEX, EVEX_K;
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def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs RC:$dst),
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(ins KRC:$mask, RC:$src),
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!strconcat(OpcodeStr,
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"\t{$src, ${dst} {${mask}} {z}|${dst} {${mask}} {z}, $src}"),
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[], d>, EVEX, EVEX_KZ;
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def rrk_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
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(ins _.RC:$src1, _.KRCWM:$mask, _.RC:$src2),
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OpcodeStr #
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"\t{$src2, ${dst} {${mask}}|${dst} {${mask}}, $src2}",
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[], _.ExeDomain>, EVEX, EVEX_K;
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def rrkz_alt : AVX512PI<opc, MRMDestReg, (outs _.RC:$dst),
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(ins _.KRCWM:$mask, _.RC:$src),
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OpcodeStr #
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"\t{$src, ${dst} {${mask}} {z}|" #
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"${dst} {${mask}} {z}, $src}",
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[], _.ExeDomain>, EVEX, EVEX_KZ;
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}
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let mayStore = 1 in {
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def mr : AVX512PI<opc, MRMDestMem, (outs), (ins memop:$dst, RC:$src),
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def mr : AVX512PI<opc, MRMDestMem, (outs), (ins _.MemOp:$dst, _.RC:$src),
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!strconcat(OpcodeStr, "\t{$src, $dst|$dst, $src}"),
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[(st_frag (OpVT RC:$src), addr:$dst)], d>, EVEX;
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[(st_frag (_.VT _.RC:$src), addr:$dst)], _.ExeDomain>, EVEX;
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def mrk : AVX512PI<opc, MRMDestMem, (outs),
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(ins memop:$dst, KRC:$mask, RC:$src),
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!strconcat(OpcodeStr,
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"\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}"),
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[], d>, EVEX, EVEX_K;
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(ins _.MemOp:$dst, _.KRCWM:$mask, _.RC:$src),
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OpcodeStr # "\t{$src, ${dst} {${mask}}|${dst} {${mask}}, $src}",
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[], _.ExeDomain>, EVEX, EVEX_K;
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}
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}
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multiclass avx512_store_vl<bits<8> opc, string OpcodeStr, string st_pat,
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string st_suff_512, string st_suff_256,
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string st_suff_128, string elty, string elsz,
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string vsz512, string vsz256, string vsz128,
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Domain d, Predicate prd> {
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multiclass avx512_store_vl< bits<8> opc, string OpcodeStr,
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AVX512VLVectorVTInfo _, Predicate prd> {
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let Predicates = [prd] in
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defm Z : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_512),
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!cast<ValueType>("v"##vsz512##elty##elsz),
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!cast<RegisterClass>("VK"##vsz512##"WM"), VR512,
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!cast<X86MemOperand>(elty##"512mem"), d>, EVEX_V512;
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defm Z : avx512_store<opc, OpcodeStr, _.info512, store>, EVEX_V512;
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let Predicates = [prd, HasVLX] in {
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defm Z256 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_256),
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!cast<ValueType>("v"##vsz256##elty##elsz),
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!cast<RegisterClass>("VK"##vsz256##"WM"), VR256X,
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!cast<X86MemOperand>(elty##"256mem"), d>, EVEX_V256;
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defm Z128 : avx512_store<opc, OpcodeStr, !cast<PatFrag>(st_pat##st_suff_128),
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!cast<ValueType>("v"##vsz128##elty##elsz),
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!cast<RegisterClass>("VK"##vsz128##"WM"), VR128X,
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!cast<X86MemOperand>(elty##"128mem"), d>, EVEX_V128;
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defm Z256 : avx512_store<opc, OpcodeStr, _.info256, store>, EVEX_V256;
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defm Z128 : avx512_store<opc, OpcodeStr, _.info128, store>, EVEX_V128;
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}
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}
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defm VMOVAPS : avx512_load_vl<0x28, "vmovaps", "alignedload", "f", "32",
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"16", "8", "4", SSEPackedSingle, HasAVX512>,
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avx512_store_vl<0x29, "vmovaps", "alignedstore",
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"512", "256", "", "f", "32", "16", "8", "4",
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SSEPackedSingle, HasAVX512>,
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multiclass avx512_alignedstore_vl<bits<8> opc, string OpcodeStr,
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AVX512VLVectorVTInfo _, Predicate prd> {
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let Predicates = [prd] in
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defm Z : avx512_store<opc, OpcodeStr, _.info512, alignedstore512>, EVEX_V512;
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let Predicates = [prd, HasVLX] in {
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defm Z256 : avx512_store<opc, OpcodeStr, _.info256, alignedstore256>,
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EVEX_V256;
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defm Z128 : avx512_store<opc, OpcodeStr, _.info128, alignedstore>,
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EVEX_V128;
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}
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}
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defm VMOVAPS : avx512_alignedload_vl<0x28, "vmovaps", avx512vl_f32_info,
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HasAVX512>,
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avx512_alignedstore_vl<0x29, "vmovaps", avx512vl_f32_info,
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HasAVX512>, PS, EVEX_CD8<32, CD8VF>;
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defm VMOVAPD : avx512_alignedload_vl<0x28, "vmovapd", avx512vl_f64_info,
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HasAVX512>,
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avx512_alignedstore_vl<0x29, "vmovapd", avx512vl_f64_info,
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HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VMOVUPS : avx512_load_vl<0x10, "vmovups", avx512vl_f32_info, HasAVX512>,
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avx512_store_vl<0x11, "vmovups", avx512vl_f32_info, HasAVX512>,
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PS, EVEX_CD8<32, CD8VF>;
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defm VMOVAPD : avx512_load_vl<0x28, "vmovapd", "alignedload", "f", "64",
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"8", "4", "2", SSEPackedDouble, HasAVX512>,
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avx512_store_vl<0x29, "vmovapd", "alignedstore",
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"512", "256", "", "f", "64", "8", "4", "2",
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SSEPackedDouble, HasAVX512>,
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PD, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VMOVUPS : avx512_load_vl<0x10, "vmovups", "load", "f", "32",
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"16", "8", "4", SSEPackedSingle, HasAVX512>,
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avx512_store_vl<0x11, "vmovups", "store", "", "", "", "f", "32",
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"16", "8", "4", SSEPackedSingle, HasAVX512>,
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PS, EVEX_CD8<32, CD8VF>;
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defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", "load", "f", "64",
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"8", "4", "2", SSEPackedDouble, HasAVX512, 0>,
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avx512_store_vl<0x11, "vmovupd", "store", "", "", "", "f", "64",
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"8", "4", "2", SSEPackedDouble, HasAVX512>,
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PD, VEX_W, EVEX_CD8<64, CD8VF>;
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defm VMOVUPD : avx512_load_vl<0x10, "vmovupd", avx512vl_f64_info, HasAVX512, 0>,
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avx512_store_vl<0x11, "vmovupd", avx512vl_f64_info, HasAVX512>,
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PD, VEX_W, EVEX_CD8<64, CD8VF>;
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def: Pat<(v8f64 (int_x86_avx512_mask_loadu_pd_512 addr:$ptr,
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(bc_v8f64 (v16i32 immAllZerosV)), GR8:$mask)),
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@ -2321,42 +2317,30 @@ def: Pat<(v8f32 (masked_load addr:$ptr, VK8WM:$mask, (v8f32 VR256:$src0))),
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(INSERT_SUBREG (v16f32 (IMPLICIT_DEF)), VR256:$src0, sub_ymm),
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(v16i1 (COPY_TO_REGCLASS VK8WM:$mask, VK16WM)), addr:$ptr)), sub_ymm))>;
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defm VMOVDQA32 : avx512_load_vl<0x6F, "vmovdqa32", "alignedload", "i", "32",
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"16", "8", "4", SSEPackedInt, HasAVX512>,
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avx512_store_vl<0x7F, "vmovdqa32", "alignedstore",
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"512", "256", "", "i", "32", "16", "8", "4",
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SSEPackedInt, HasAVX512>,
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PD, EVEX_CD8<32, CD8VF>;
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defm VMOVDQA32 : avx512_alignedload_vl<0x6F, "vmovdqa32", avx512vl_i32_info,
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HasAVX512>,
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avx512_alignedstore_vl<0x7F, "vmovdqa32", avx512vl_i32_info,
|
||||
HasAVX512>, PD, EVEX_CD8<32, CD8VF>;
|
||||
|
||||
defm VMOVDQA64 : avx512_load_vl<0x6F, "vmovdqa64", "alignedload", "i", "64",
|
||||
"8", "4", "2", SSEPackedInt, HasAVX512>,
|
||||
avx512_store_vl<0x7F, "vmovdqa64", "alignedstore",
|
||||
"512", "256", "", "i", "64", "8", "4", "2",
|
||||
SSEPackedInt, HasAVX512>,
|
||||
PD, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
defm VMOVDQA64 : avx512_alignedload_vl<0x6F, "vmovdqa64", avx512vl_i64_info,
|
||||
HasAVX512>,
|
||||
avx512_alignedstore_vl<0x7F, "vmovdqa64", avx512vl_i64_info,
|
||||
HasAVX512>, PD, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", "load", "i", "8",
|
||||
"64", "32", "16", SSEPackedInt, HasBWI>,
|
||||
avx512_store_vl<0x7F, "vmovdqu8", "store", "", "", "",
|
||||
"i", "8", "64", "32", "16", SSEPackedInt,
|
||||
defm VMOVDQU8 : avx512_load_vl<0x6F, "vmovdqu8", avx512vl_i8_info, HasBWI>,
|
||||
avx512_store_vl<0x7F, "vmovdqu8", avx512vl_i8_info,
|
||||
HasBWI>, XD, EVEX_CD8<8, CD8VF>;
|
||||
|
||||
defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", "load", "i", "16",
|
||||
"32", "16", "8", SSEPackedInt, HasBWI>,
|
||||
avx512_store_vl<0x7F, "vmovdqu16", "store", "", "", "",
|
||||
"i", "16", "32", "16", "8", SSEPackedInt,
|
||||
defm VMOVDQU16 : avx512_load_vl<0x6F, "vmovdqu16", avx512vl_i16_info, HasBWI>,
|
||||
avx512_store_vl<0x7F, "vmovdqu16", avx512vl_i16_info,
|
||||
HasBWI>, XD, VEX_W, EVEX_CD8<16, CD8VF>;
|
||||
|
||||
defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", "load", "i", "32",
|
||||
"16", "8", "4", SSEPackedInt, HasAVX512>,
|
||||
avx512_store_vl<0x7F, "vmovdqu32", "store", "", "", "",
|
||||
"i", "32", "16", "8", "4", SSEPackedInt,
|
||||
defm VMOVDQU32 : avx512_load_vl<0x6F, "vmovdqu32", avx512vl_i32_info, HasAVX512>,
|
||||
avx512_store_vl<0x7F, "vmovdqu32", avx512vl_i32_info,
|
||||
HasAVX512>, XS, EVEX_CD8<32, CD8VF>;
|
||||
|
||||
defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", "load", "i", "64",
|
||||
"8", "4", "2", SSEPackedInt, HasAVX512>,
|
||||
avx512_store_vl<0x7F, "vmovdqu64", "store", "", "", "",
|
||||
"i", "64", "8", "4", "2", SSEPackedInt,
|
||||
defm VMOVDQU64 : avx512_load_vl<0x6F, "vmovdqu64", avx512vl_i64_info, HasAVX512>,
|
||||
avx512_store_vl<0x7F, "vmovdqu64", avx512vl_i64_info,
|
||||
HasAVX512>, XS, VEX_W, EVEX_CD8<64, CD8VF>;
|
||||
|
||||
def: Pat<(v16i32 (int_x86_avx512_mask_loadu_d_512 addr:$ptr,
|
||||
|
||||
Loading…
Reference in New Issue
Block a user