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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-18 12:29:21 +00:00
Eliminate use of getNode that takes a vector.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@29614 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -121,7 +121,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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}
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}
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOpChains);
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Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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// Build a sequence of copy-to-reg nodes chained together with token chain
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// and flag operands which copy the outgoing args into the appropriate regs.
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@ -261,7 +261,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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}
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//Set up a token factor with all the stack traffic
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Root = DAG.getNode(ISD::TokenFactor, MVT::Other, LS);
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Root = DAG.getNode(ISD::TokenFactor, MVT::Other, &LS[0], LS.size());
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}
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ArgValues.push_back(Root);
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@ -396,7 +396,7 @@ IA64TargetLowering::LowerCallTo(SDOperand Chain,
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// Emit all stores, make sure they occur before any copies into physregs.
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if (!Stores.empty())
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Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, Stores);
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Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, &Stores[0],Stores.size());
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static const unsigned IntArgRegs[] = {
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IA64::out0, IA64::out1, IA64::out2, IA64::out3,
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@ -895,7 +895,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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// If this function is vararg, store any remaining integer argument regs
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// to their spots on the stack so that they may be loaded by deferencing the
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// result of va_next.
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std::vector<SDOperand> MemOps;
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SmallVector<SDOperand, 8> MemOps;
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for (; GPR_idx != Num_GPR_Regs; ++GPR_idx) {
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unsigned VReg = RegMap->createVirtualRegister(&PPC::GPRCRegClass);
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MF.addLiveIn(GPR[GPR_idx], VReg);
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@ -908,7 +908,7 @@ static SDOperand LowerFORMAL_ARGUMENTS(SDOperand Op, SelectionDAG &DAG,
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FIN = DAG.getNode(ISD::ADD, PtrOff.getValueType(), FIN, PtrOff);
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}
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if (!MemOps.empty())
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Root = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOps);
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Root = DAG.getNode(ISD::TokenFactor, MVT::Other,&MemOps[0],MemOps.size());
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}
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ArgValues.push_back(Root);
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@ -1011,7 +1011,7 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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const unsigned *GPR = isPPC64 ? GPR_64 : GPR_32;
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std::vector<std::pair<unsigned, SDOperand> > RegsToPass;
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std::vector<SDOperand> MemOpChains;
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SmallVector<SDOperand, 8> MemOpChains;
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for (unsigned i = 0; i != NumOps; ++i) {
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SDOperand Arg = Op.getOperand(5+2*i);
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@ -1096,7 +1096,8 @@ static SDOperand LowerCALL(SDOperand Op, SelectionDAG &DAG) {
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}
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}
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if (!MemOpChains.empty())
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Chain = DAG.getNode(ISD::TokenFactor, MVT::Other, MemOpChains);
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Chain = DAG.getNode(ISD::TokenFactor, MVT::Other,
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&MemOpChains[0], MemOpChains.size());
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// Build a sequence of copy-to-reg nodes chained together with token chain
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// and flag operands which copy the outgoing args into the appropriate regs.
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@ -1609,8 +1610,10 @@ static SDOperand BuildSplatI(int Val, unsigned SplatSize, MVT::ValueType VT,
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// Build a canonical splat for this value.
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SDOperand Elt = DAG.getConstant(Val, MVT::getVectorBaseType(CanonicalVT));
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std::vector<SDOperand> Ops(MVT::getVectorNumElements(CanonicalVT), Elt);
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SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT, Ops);
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SmallVector<SDOperand, 8> Ops;
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Ops.assign(MVT::getVectorNumElements(CanonicalVT), Elt);
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SDOperand Res = DAG.getNode(ISD::BUILD_VECTOR, CanonicalVT,
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&Ops[0], Ops.size());
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return DAG.getNode(ISD::BIT_CONVERT, VT, Res);
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}
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@ -1643,11 +1646,11 @@ static SDOperand BuildVSLDOI(SDOperand LHS, SDOperand RHS, unsigned Amt,
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LHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, LHS);
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RHS = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, RHS);
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std::vector<SDOperand> Ops;
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SDOperand Ops[16];
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for (unsigned i = 0; i != 16; ++i)
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Ops.push_back(DAG.getConstant(i+Amt, MVT::i32));
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Ops[i] = DAG.getConstant(i+Amt, MVT::i32);
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SDOperand T = DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, LHS, RHS,
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DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
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DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops,16));
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return DAG.getNode(ISD::BIT_CONVERT, VT, T);
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}
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@ -1879,12 +1882,12 @@ static SDOperand GeneratePerfectShuffle(unsigned PFEntry, SDOperand LHS,
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case OP_VSLDOI12:
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return BuildVSLDOI(OpLHS, OpRHS, 12, OpLHS.getValueType(), DAG);
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}
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std::vector<SDOperand> Ops;
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SDOperand Ops[16];
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for (unsigned i = 0; i != 16; ++i)
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Ops.push_back(DAG.getConstant(ShufIdxs[i], MVT::i32));
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Ops[i] = DAG.getConstant(ShufIdxs[i], MVT::i32);
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return DAG.getNode(ISD::VECTOR_SHUFFLE, OpLHS.getValueType(), OpLHS, OpRHS,
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DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
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DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
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}
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/// LowerVECTOR_SHUFFLE - Return the code we lower for VECTOR_SHUFFLE. If this
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@ -1992,7 +1995,7 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
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MVT::ValueType EltVT = MVT::getVectorBaseType(V1.getValueType());
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unsigned BytesPerElement = MVT::getSizeInBits(EltVT)/8;
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std::vector<SDOperand> ResultMask;
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SmallVector<SDOperand, 16> ResultMask;
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for (unsigned i = 0, e = PermMask.getNumOperands(); i != e; ++i) {
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unsigned SrcElt;
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if (PermMask.getOperand(i).getOpcode() == ISD::UNDEF)
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@ -2005,7 +2008,8 @@ static SDOperand LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
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MVT::i8));
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}
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SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, ResultMask);
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SDOperand VPermMask = DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8,
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&ResultMask[0], ResultMask.size());
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return DAG.getNode(PPCISD::VPERM, V1.getValueType(), V1, V2, VPermMask);
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}
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@ -2180,14 +2184,13 @@ static SDOperand LowerMUL(SDOperand Op, SelectionDAG &DAG) {
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OddParts = DAG.getNode(ISD::BIT_CONVERT, MVT::v16i8, OddParts);
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// Merge the results together.
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std::vector<SDOperand> Ops;
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SDOperand Ops[16];
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for (unsigned i = 0; i != 8; ++i) {
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Ops.push_back(DAG.getConstant(2*i+1, MVT::i8));
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Ops.push_back(DAG.getConstant(2*i+1+16, MVT::i8));
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Ops[i*2 ] = DAG.getConstant(2*i+1, MVT::i8);
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Ops[i*2+1] = DAG.getConstant(2*i+1+16, MVT::i8);
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}
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return DAG.getNode(ISD::VECTOR_SHUFFLE, MVT::v16i8, EvenParts, OddParts,
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DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops));
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DAG.getNode(ISD::BUILD_VECTOR, MVT::v16i8, Ops, 16));
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} else {
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assert(0 && "Unknown mul to lower!");
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abort();
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@ -2365,7 +2365,8 @@ X86TargetLowering::LowerBUILD_VECTOR(SDOperand Op, SelectionDAG &DAG) {
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MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
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else
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MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
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SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
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SDOperand ShufMask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
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&MaskVec[0], MaskVec.size());
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V[0], V[1], ShufMask);
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}
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@ -2501,14 +2502,15 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
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MaskVec.push_back(PermMask.getOperand(i));
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for (unsigned i = 4; i != 8; ++i)
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MaskVec.push_back(DAG.getConstant(i, BaseVT));
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SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
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SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
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&MaskVec[0], MaskVec.size());
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V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
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MaskVec.clear();
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for (unsigned i = 0; i != 4; ++i)
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MaskVec.push_back(DAG.getConstant(i, BaseVT));
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for (unsigned i = 4; i != 8; ++i)
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MaskVec.push_back(PermMask.getOperand(i));
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Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec);
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Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, &MaskVec[0],MaskVec.size());
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2, Mask);
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}
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} else {
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@ -2558,7 +2560,8 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
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}
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if (NumLo <= 2 && NumHi <= 2) {
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V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
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DAG.getNode(ISD::BUILD_VECTOR, MaskVT, Mask1));
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DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
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&Mask1[0], Mask1.size()));
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for (unsigned i = 0; i != NumElems; ++i) {
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if (Locs[i].first == -1)
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continue;
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@ -2570,7 +2573,8 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
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}
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V1,
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DAG.getNode(ISD::BUILD_VECTOR, MaskVT, Mask2));
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DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
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&Mask2[0], Mask2.size()));
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}
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// Break it into (shuffle shuffle_hi, shuffle_lo).
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@ -2604,10 +2608,12 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
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SDOperand LoShuffle =
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DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
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DAG.getNode(ISD::BUILD_VECTOR, MaskVT, LoMask));
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DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
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&LoMask[0], LoMask.size()));
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SDOperand HiShuffle =
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DAG.getNode(ISD::VECTOR_SHUFFLE, VT, V1, V2,
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DAG.getNode(ISD::BUILD_VECTOR, MaskVT, HiMask));
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DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
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&HiMask[0], HiMask.size()));
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std::vector<SDOperand> MaskOps;
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for (unsigned i = 0; i != NumElems; ++i) {
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if (Locs[i].first == -1) {
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@ -2618,7 +2624,8 @@ X86TargetLowering::LowerVECTOR_SHUFFLE(SDOperand Op, SelectionDAG &DAG) {
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}
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}
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, LoShuffle, HiShuffle,
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DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskOps));
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DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
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&MaskOps[0], MaskOps.size()));
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}
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return SDOperand();
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@ -2651,7 +2658,8 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
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IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
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IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
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IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
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SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, IdxVec);
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SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
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&IdxVec[0], IdxVec.size());
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Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
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Vec, Vec, Mask);
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
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@ -2669,7 +2677,8 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
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std::vector<SDOperand> IdxVec;
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IdxVec.push_back(DAG.getConstant(1, MVT::getVectorBaseType(MaskVT)));
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IdxVec.push_back(DAG.getNode(ISD::UNDEF, MVT::getVectorBaseType(MaskVT)));
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SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT, IdxVec);
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SDOperand Mask = DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
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&IdxVec[0], IdxVec.size());
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Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, Vec.getValueType(),
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Vec, DAG.getNode(ISD::UNDEF, Vec.getValueType()), Mask);
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return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, VT, Vec,
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@ -2706,7 +2715,8 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDOperand Op, SelectionDAG &DAG) {
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for (unsigned i = 1; i <= 3; ++i)
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MaskVec.push_back(DAG.getConstant(i, BaseVT));
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return DAG.getNode(ISD::VECTOR_SHUFFLE, VT, N0, N1,
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DAG.getNode(ISD::BUILD_VECTOR, MaskVT, MaskVec));
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DAG.getNode(ISD::BUILD_VECTOR, MaskVT,
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&MaskVec[0], MaskVec.size()));
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} else {
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// Use two pinsrw instructions to insert a 32 bit value.
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Idx <<= 1;
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