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Add an additional pattern for BLCI since opt can turn (not (add x, 1)) into (sub -2, x).

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@192037 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Craig Topper 2013-10-05 17:17:53 +00:00
parent 5e195a4c8d
commit e2522fd06c
2 changed files with 26 additions and 0 deletions
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6
lib/Target/X86/X86InstrInfo.td
View File

@ -2014,6 +2014,12 @@ let Predicates = [HasTBM] in {
def : Pat<(or GR64:$src, (not (add GR64:$src, 1))),
(BLCI_64rr GR64:$src)>;
// Extra patterns because opt can optimize the above patterns to this.
def : Pat<(or GR32:$src, (sub -2, GR32:$src)),
(BLCI_32rr GR32:$src)>;
def : Pat<(or GR64:$src, (sub -2, GR64:$src)),
(BLCI_64rr GR64:$src)>;
def : Pat<(and (not GR32:$src), (add GR32:$src, 1)),
(BLCIC_32rr GR32:$src)>;
def : Pat<(and (not GR64:$src), (add GR64:$src, 1)),

20
test/CodeGen/X86/tbm_patterns.ll
View File

@ -84,6 +84,26 @@ entry:
ret i64 %2
}
define i32 @test_x86_tbm_blci_u32_b(i32 %a) nounwind readnone {
entry:
; CHECK-LABEL: test_x86_tbm_blci_u32_b:
; CHECK-NOT: mov
; CHECK: blci %
%0 = sub i32 -2, %a
%1 = or i32 %0, %a
ret i32 %1
}
define i64 @test_x86_tbm_blci_u64_b(i64 %a) nounwind readnone {
entry:
; CHECK-LABEL: test_x86_tbm_blci_u64_b:
; CHECK-NOT: mov
; CHECK: blci %
%0 = sub i64 -2, %a
%1 = or i64 %0, %a
ret i64 %1
}
define i32 @test_x86_tbm_blcic_u32(i32 %a) nounwind readnone {
entry:
; CHECK-LABEL: test_x86_tbm_blcic_u32: