mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2025-01-14 16:33:28 +00:00
R600/SI: cleanup literal handling v3
Seems to be allot simpler, and also paves the
way for further improvements.
v2: rebased on master, use 0 in BUFFER_LOAD_FORMAT_XYZW,
use VGPR0 in dummy EXP, avoid compiler warning, break
after encoding the first literal.
v3: correctly use V_ADD_F32_e64
This is a candidate for the stable branch.
Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@175354 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Christian Konig
parent
8e4eebcecf
commit
e25e490793
@ -30,7 +30,6 @@ FunctionPass *createSIAnnotateControlFlowPass();
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FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm);
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FunctionPass *createSILowerControlFlowPass(TargetMachine &tm);
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FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS);
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FunctionPass *createSILowerLiteralConstantsPass(TargetMachine &tm);
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FunctionPass *createSIInsertWaits(TargetMachine &tm);
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// Passes common to R600 and SI
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@ -91,8 +91,6 @@ void AMDGPUAsmPrinter::EmitProgramInfo(MachineFunction &MF) {
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switch (reg) {
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default: break;
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case AMDGPU::EXEC:
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case AMDGPU::SI_LITERAL_CONSTANT:
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case AMDGPU::SREG_LIT_0:
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case AMDGPU::M0:
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continue;
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}
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@ -145,7 +145,6 @@ bool AMDGPUPassConfig::addPreEmitPass() {
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addPass(&FinalizeMachineBundlesID);
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addPass(createR600LowerConstCopy(*TM));
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} else {
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addPass(createSILowerLiteralConstantsPass(*TM));
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addPass(createSILowerControlFlowPass(*TM));
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}
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@ -27,6 +27,13 @@
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using namespace llvm;
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namespace {
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/// \brief Helper type used in encoding
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typedef union {
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int32_t I;
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float F;
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} IntFloatUnion;
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class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
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SIMCCodeEmitter(const SIMCCodeEmitter &); // DO NOT IMPLEMENT
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void operator=(const SIMCCodeEmitter &); // DO NOT IMPLEMENT
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@ -35,6 +42,15 @@ class SIMCCodeEmitter : public AMDGPUMCCodeEmitter {
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const MCSubtargetInfo &STI;
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MCContext &Ctx;
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/// \brief Encode a sequence of registers with the correct alignment.
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unsigned GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const;
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/// \brief Can this operand also contain immediate values?
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bool isSrcOperand(const MCInstrDesc &Desc, unsigned OpNo) const;
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/// \brief Encode an fp or int literal
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uint32_t getLitEncoding(const MCOperand &MO) const;
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public:
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SIMCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri,
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const MCSubtargetInfo &sti, MCContext &ctx)
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@ -50,11 +66,6 @@ public:
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virtual uint64_t getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const;
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public:
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/// \brief Encode a sequence of registers with the correct alignment.
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unsigned GPRAlign(const MCInst &MI, unsigned OpNo, unsigned shift) const;
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/// \brief Encoding for when 2 consecutive registers are used
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virtual unsigned GPR2AlignEncode(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixup) const;
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@ -73,39 +84,131 @@ MCCodeEmitter *llvm::createSIMCCodeEmitter(const MCInstrInfo &MCII,
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return new SIMCCodeEmitter(MCII, MRI, STI, Ctx);
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}
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bool SIMCCodeEmitter::isSrcOperand(const MCInstrDesc &Desc,
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unsigned OpNo) const {
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unsigned RegClass = Desc.OpInfo[OpNo].RegClass;
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return (AMDGPU::SSrc_32RegClassID == RegClass) ||
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(AMDGPU::SSrc_64RegClassID == RegClass) ||
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(AMDGPU::VSrc_32RegClassID == RegClass) ||
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(AMDGPU::VSrc_64RegClassID == RegClass);
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}
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uint32_t SIMCCodeEmitter::getLitEncoding(const MCOperand &MO) const {
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IntFloatUnion Imm;
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if (MO.isImm())
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Imm.I = MO.getImm();
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else if (MO.isFPImm())
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Imm.F = MO.getFPImm();
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else
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return ~0;
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if (Imm.I >= 0 && Imm.I <= 64)
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return 128 + Imm.I;
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if (Imm.I >= -16 && Imm.I <= -1)
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return 192 + abs(Imm.I);
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if (Imm.F == 0.5f)
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return 240;
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if (Imm.F == -0.5f)
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return 241;
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if (Imm.F == 1.0f)
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return 242;
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if (Imm.F == -1.0f)
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return 243;
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if (Imm.F == 2.0f)
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return 244;
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if (Imm.F == -2.0f)
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return 245;
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if (Imm.F == 4.0f)
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return 246;
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if (Imm.F == 4.0f)
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return 247;
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return 255;
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}
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void SIMCCodeEmitter::EncodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups) const {
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uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups);
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unsigned bytes = MCII.get(MI.getOpcode()).getSize();
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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unsigned bytes = Desc.getSize();
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for (unsigned i = 0; i < bytes; i++) {
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OS.write((uint8_t) ((Encoding >> (8 * i)) & 0xff));
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}
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if (bytes > 4)
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return;
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// Check for additional literals in SRC0/1/2 (Op 1/2/3)
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for (unsigned i = 0, e = MI.getNumOperands(); i < e; ++i) {
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// Check if this operand should be encoded as [SV]Src
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if (!isSrcOperand(Desc, i))
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continue;
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// Is this operand a literal immediate?
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const MCOperand &Op = MI.getOperand(i);
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if (getLitEncoding(Op) != 255)
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continue;
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// Yes! Encode it
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IntFloatUnion Imm;
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if (Op.isImm())
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Imm.I = Op.getImm();
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else
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Imm.F = Op.getFPImm();
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for (unsigned j = 0; j < 4; j++) {
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OS.write((uint8_t) ((Imm.I >> (8 * j)) & 0xff));
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}
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// Only one literal value allowed
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break;
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}
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}
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uint64_t SIMCCodeEmitter::getMachineOpValue(const MCInst &MI,
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const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups) const {
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if (MO.isReg()) {
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if (MO.isReg())
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return MRI.getEncodingValue(MO.getReg());
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} else if (MO.isImm()) {
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return MO.getImm();
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} else if (MO.isFPImm()) {
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// XXX: Not all instructions can use inline literals
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// XXX: We should make sure this is a 32-bit constant
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union {
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float F;
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uint32_t I;
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} Imm;
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Imm.F = MO.getFPImm();
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return Imm.I;
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} else if (MO.isExpr()) {
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if (MO.isExpr()) {
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const MCExpr *Expr = MO.getExpr();
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MCFixupKind Kind = MCFixupKind(FK_PCRel_4);
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Fixups.push_back(MCFixup::Create(0, Expr, Kind, MI.getLoc()));
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return 0;
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} else{
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llvm_unreachable("Encoding of this operand type is not supported yet.");
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}
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// Figure out the operand number, needed for isSrcOperand check
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unsigned OpNo = 0;
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for (unsigned e = MI.getNumOperands(); OpNo < e; ++OpNo) {
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if (&MO == &MI.getOperand(OpNo))
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break;
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}
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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if (isSrcOperand(Desc, OpNo)) {
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uint32_t Enc = getLitEncoding(MO);
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if (Enc != ~0U && (Enc != 255 || Desc.getSize() == 4))
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return Enc;
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} else if (MO.isImm())
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return MO.getImm();
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llvm_unreachable("Encoding of this operand type is not supported yet.");
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return 0;
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}
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@ -118,6 +221,7 @@ unsigned SIMCCodeEmitter::GPRAlign(const MCInst &MI, unsigned OpNo,
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unsigned regCode = MRI.getEncodingValue(MI.getOperand(OpNo).getReg());
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return (regCode & 0xff) >> shift;
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}
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unsigned SIMCCodeEmitter::GPR2AlignEncode(const MCInst &MI,
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unsigned OpNo ,
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SmallVectorImpl<MCFixup> &Fixup) const {
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@ -77,8 +77,8 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
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BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_ADD_F32_e64))
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.addOperand(MI->getOperand(0))
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.addOperand(MI->getOperand(1))
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.addReg(AMDGPU::SREG_LIT_0)
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.addReg(AMDGPU::SREG_LIT_0)
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.addImm(0x80) // SRC1
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.addImm(0x80) // SRC2
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.addImm(0) // ABS
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.addImm(1) // CLAMP
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.addImm(0) // OMOD
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@ -90,8 +90,8 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
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BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_ADD_F32_e64))
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.addOperand(MI->getOperand(0))
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.addOperand(MI->getOperand(1))
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.addReg(AMDGPU::SREG_LIT_0)
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.addReg(AMDGPU::SREG_LIT_0)
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.addImm(0x80) // SRC1
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.addImm(0x80) // SRC2
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.addImm(1) // ABS
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.addImm(0) // CLAMP
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.addImm(0) // OMOD
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@ -103,8 +103,8 @@ MachineBasicBlock * SITargetLowering::EmitInstrWithCustomInserter(
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BuildMI(*BB, I, BB->findDebugLoc(I), TII->get(AMDGPU::V_ADD_F32_e64))
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.addOperand(MI->getOperand(0))
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.addOperand(MI->getOperand(1))
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.addReg(AMDGPU::SREG_LIT_0)
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.addReg(AMDGPU::SREG_LIT_0)
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.addImm(0x80) // SRC1
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.addImm(0x80) // SRC2
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.addImm(0) // ABS
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.addImm(0) // CLAMP
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.addImm(0) // OMOD
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@ -176,7 +176,7 @@ void SITargetLowering::LowerSI_V_CNDLT(MachineInstr *MI, MachineBasicBlock &BB,
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BuildMI(BB, I, BB.findDebugLoc(I),
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TII->get(AMDGPU::V_CMP_GT_F32_e32),
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VCC)
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.addReg(AMDGPU::SREG_LIT_0)
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.addImm(0)
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.addOperand(MI->getOperand(1));
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BuildMI(BB, I, BB.findDebugLoc(I), TII->get(AMDGPU::V_CNDMASK_B32_e32))
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@ -68,7 +68,7 @@ SIInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
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MachineInstr * SIInstrInfo::getMovImmInstr(MachineFunction *MF, unsigned DstReg,
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int64_t Imm) const {
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MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_IMM_I32), DebugLoc());
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MachineInstr * MI = MF->CreateMachineInstr(get(AMDGPU::V_MOV_B32_e32), DebugLoc());
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MachineInstrBuilder MIB(*MF, MI);
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MIB.addReg(DstReg, RegState::Define);
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MIB.addImm(Imm);
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@ -84,9 +84,6 @@ bool SIInstrInfo::isMov(unsigned Opcode) const {
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case AMDGPU::S_MOV_B64:
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case AMDGPU::V_MOV_B32_e32:
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case AMDGPU::V_MOV_B32_e64:
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case AMDGPU::V_MOV_IMM_F32:
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case AMDGPU::V_MOV_IMM_I32:
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case AMDGPU::S_MOV_IMM_I32:
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return true;
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}
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}
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@ -1018,45 +1018,6 @@ def S_BFE_I64 : SOP2_64 <0x0000002a, "S_BFE_I64", []>;
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//def S_CBRANCH_G_FORK : SOP2_ <0x0000002b, "S_CBRANCH_G_FORK", []>;
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def S_ABSDIFF_I32 : SOP2_32 <0x0000002c, "S_ABSDIFF_I32", []>;
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class V_MOV_IMM <ValueType type, Operand immType, SDNode immNode> : InstSI <
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(outs VReg_32:$dst),
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(ins immType:$src0),
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"V_MOV_IMM",
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[(set VReg_32:$dst, (type immNode:$src0))]
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>;
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let isCodeGenOnly = 1, isPseudo = 1 in {
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def V_MOV_IMM_I32 : V_MOV_IMM<i32, i32imm, imm>;
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def V_MOV_IMM_F32 : V_MOV_IMM<f32, f32imm, fpimm>;
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def S_MOV_IMM_I32 : InstSI <
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(outs SReg_32:$dst),
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(ins i32imm:$src0),
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"S_MOV_IMM_I32",
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[(set SReg_32:$dst, (imm:$src0))]
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>;
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} // End isCodeGenOnly, isPseudo = 1
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// i64 immediates aren't supported in hardware, split it into two 32bit values
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def : Pat <
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(i64 imm:$imm),
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(INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(S_MOV_IMM_I32 (LO32 imm:$imm)), sub0),
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(S_MOV_IMM_I32 (HI32 imm:$imm)), sub1)
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>;
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class SI_LOAD_LITERAL<Operand ImmType> :
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Enc32 <(outs), (ins ImmType:$imm), "LOAD_LITERAL $imm", []> {
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bits<32> imm;
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let Inst{31-0} = imm;
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}
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def SI_LOAD_LITERAL_I32 : SI_LOAD_LITERAL<i32imm>;
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def SI_LOAD_LITERAL_F32 : SI_LOAD_LITERAL<f32imm>;
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let isCodeGenOnly = 1, isPseudo = 1 in {
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def SET_M0 : InstSI <
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@ -1173,7 +1134,7 @@ def SI_KILL : InstSI <
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def : Pat <
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(int_AMDGPU_kilp),
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(SI_KILL (V_MOV_IMM_I32 0xbf800000))
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(SI_KILL (V_MOV_B32_e32 0xbf800000))
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>;
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/* int_SI_vs_load_input */
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@ -1182,7 +1143,7 @@ def : Pat<
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VReg_32:$buf_idx_vgpr),
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(BUFFER_LOAD_FORMAT_XYZW imm:$attr_offset, 0, 1, 0, 0, 0,
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VReg_32:$buf_idx_vgpr, SReg_128:$tlst,
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0, 0, (i32 SREG_LIT_0))
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0, 0, 0)
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>;
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/* int_SI_export */
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@ -1319,6 +1280,38 @@ def : Pat <
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(COPY_TO_REGCLASS SReg_64:$vcc, VCCReg)
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>;
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/********** ================== **********/
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/********** Immediate Patterns **********/
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/********** ================== **********/
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def : Pat <
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(i32 imm:$imm),
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(V_MOV_B32_e32 imm:$imm)
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>;
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def : Pat <
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(f32 fpimm:$imm),
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(V_MOV_B32_e32 fpimm:$imm)
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>;
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def : Pat <
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(i32 imm:$imm),
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(S_MOV_B32 imm:$imm)
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>;
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def : Pat <
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(f32 fpimm:$imm),
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(S_MOV_B32 fpimm:$imm)
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>;
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// i64 immediates aren't supported in hardware, split it into two 32bit values
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def : Pat <
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(i64 imm:$imm),
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(INSERT_SUBREG (INSERT_SUBREG (i64 (IMPLICIT_DEF)),
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(S_MOV_B32 (i32 (LO32 imm:$imm))), sub0),
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(S_MOV_B32 (i32 (HI32 imm:$imm))), sub1)
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>;
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/********** ===================== **********/
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/********** Interpolation Paterns **********/
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/********** ===================== **********/
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@ -1397,12 +1390,12 @@ def : Pat<
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def : Pat <
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(fcos VSrc_32:$src0),
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(V_COS_F32_e32 (V_MUL_F32_e32 VSrc_32:$src0, (V_MOV_IMM_I32 CONST.TWO_PI_INV)))
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(V_COS_F32_e32 (V_MUL_F32_e32 VSrc_32:$src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
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>;
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def : Pat <
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(fsin VSrc_32:$src0),
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(V_SIN_F32_e32 (V_MUL_F32_e32 VSrc_32:$src0, (V_MOV_IMM_I32 CONST.TWO_PI_INV)))
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(V_SIN_F32_e32 (V_MUL_F32_e32 VSrc_32:$src0, (V_MOV_B32_e32 CONST.TWO_PI_INV)))
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>;
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def : Pat <
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@ -1448,7 +1441,7 @@ multiclass SMRD_Pattern <SMRD Instr_IMM, SMRD Instr_SGPR, ValueType vt> {
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// 2. Offset loaded in an 32bit SGPR
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def : Pat <
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(constant_load (SIadd64bit32bit SReg_64:$sbase, imm:$offset)),
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(vt (Instr_SGPR SReg_64:$sbase, (S_MOV_IMM_I32 imm:$offset)))
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(vt (Instr_SGPR SReg_64:$sbase, (S_MOV_B32 imm:$offset)))
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>;
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// 3. No offset at all
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@ -158,10 +158,10 @@ void SILowerControlFlowPass::SkipIfDead(MachineInstr &MI) {
|
||||
.addImm(0)
|
||||
.addImm(1)
|
||||
.addImm(1)
|
||||
.addReg(AMDGPU::SREG_LIT_0)
|
||||
.addReg(AMDGPU::SREG_LIT_0)
|
||||
.addReg(AMDGPU::SREG_LIT_0)
|
||||
.addReg(AMDGPU::SREG_LIT_0);
|
||||
.addReg(AMDGPU::VGPR0)
|
||||
.addReg(AMDGPU::VGPR0)
|
||||
.addReg(AMDGPU::VGPR0)
|
||||
.addReg(AMDGPU::VGPR0);
|
||||
|
||||
// ... and terminate wavefront
|
||||
BuildMI(MBB, Insert, DL, TII->get(AMDGPU::S_ENDPGM));
|
||||
@ -296,7 +296,7 @@ void SILowerControlFlowPass::Kill(MachineInstr &MI) {
|
||||
|
||||
// Clear this pixel from the exec mask if the operand is negative
|
||||
BuildMI(MBB, &MI, DL, TII->get(AMDGPU::V_CMPX_LE_F32_e32), AMDGPU::VCC)
|
||||
.addReg(AMDGPU::SREG_LIT_0)
|
||||
.addImm(0)
|
||||
.addOperand(MI.getOperand(0));
|
||||
|
||||
MI.eraseFromParent();
|
||||
|
||||
@ -1,107 +0,0 @@
|
||||
//===-- SILowerLiteralConstants.cpp - Lower intrs using literal constants--===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file is distributed under the University of Illinois Open Source
|
||||
// License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
/// \file
|
||||
/// \brief This pass performs the following transformation on instructions with
|
||||
/// literal constants:
|
||||
///
|
||||
/// %VGPR0 = V_MOV_IMM_I32 1
|
||||
///
|
||||
/// becomes:
|
||||
///
|
||||
/// BUNDLE
|
||||
/// * %VGPR = V_MOV_B32_32 SI_LITERAL_CONSTANT
|
||||
/// * SI_LOAD_LITERAL 1
|
||||
///
|
||||
/// The resulting sequence matches exactly how the hardware handles immediate
|
||||
/// operands, so this transformation greatly simplifies the code generator.
|
||||
///
|
||||
/// Only the *_MOV_IMM_* support immediate operands at the moment, but when
|
||||
/// support for immediate operands is added to other instructions, they
|
||||
/// will be lowered here as well.
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "AMDGPU.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/MachineFunctionPass.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "llvm/CodeGen/MachineInstrBundle.h"
|
||||
|
||||
using namespace llvm;
|
||||
|
||||
namespace {
|
||||
|
||||
class SILowerLiteralConstantsPass : public MachineFunctionPass {
|
||||
|
||||
private:
|
||||
static char ID;
|
||||
const TargetInstrInfo *TII;
|
||||
|
||||
public:
|
||||
SILowerLiteralConstantsPass(TargetMachine &tm) :
|
||||
MachineFunctionPass(ID), TII(tm.getInstrInfo()) { }
|
||||
|
||||
virtual bool runOnMachineFunction(MachineFunction &MF);
|
||||
|
||||
const char *getPassName() const {
|
||||
return "SI Lower literal constants pass";
|
||||
}
|
||||
};
|
||||
|
||||
} // End anonymous namespace
|
||||
|
||||
char SILowerLiteralConstantsPass::ID = 0;
|
||||
|
||||
FunctionPass *llvm::createSILowerLiteralConstantsPass(TargetMachine &tm) {
|
||||
return new SILowerLiteralConstantsPass(tm);
|
||||
}
|
||||
|
||||
bool SILowerLiteralConstantsPass::runOnMachineFunction(MachineFunction &MF) {
|
||||
for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end();
|
||||
BB != BB_E; ++BB) {
|
||||
MachineBasicBlock &MBB = *BB;
|
||||
for (MachineBasicBlock::iterator I = MBB.begin(), Next = llvm::next(I);
|
||||
I != MBB.end(); I = Next) {
|
||||
Next = llvm::next(I);
|
||||
MachineInstr &MI = *I;
|
||||
switch (MI.getOpcode()) {
|
||||
default: break;
|
||||
case AMDGPU::S_MOV_IMM_I32:
|
||||
case AMDGPU::V_MOV_IMM_F32:
|
||||
case AMDGPU::V_MOV_IMM_I32: {
|
||||
unsigned MovOpcode;
|
||||
unsigned LoadLiteralOpcode;
|
||||
MachineOperand LiteralOp = MI.getOperand(1);
|
||||
if (AMDGPU::VReg_32RegClass.contains(MI.getOperand(0).getReg())) {
|
||||
MovOpcode = AMDGPU::V_MOV_B32_e32;
|
||||
} else {
|
||||
MovOpcode = AMDGPU::S_MOV_B32;
|
||||
}
|
||||
if (LiteralOp.isImm()) {
|
||||
LoadLiteralOpcode = AMDGPU::SI_LOAD_LITERAL_I32;
|
||||
} else {
|
||||
LoadLiteralOpcode = AMDGPU::SI_LOAD_LITERAL_F32;
|
||||
}
|
||||
MIBundleBuilder Bundle(MBB, I);
|
||||
Bundle
|
||||
.append(BuildMI(MF, MBB.findDebugLoc(I), TII->get(MovOpcode),
|
||||
MI.getOperand(0).getReg())
|
||||
.addReg(AMDGPU::SI_LITERAL_CONSTANT))
|
||||
.append(BuildMI(MF, MBB.findDebugLoc(I),
|
||||
TII->get(LoadLiteralOpcode))
|
||||
.addOperand(MI.getOperand(1)));
|
||||
llvm::finalizeBundle(MBB, Bundle.begin());
|
||||
MI.eraseFromParent();
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
@ -22,8 +22,6 @@ def EXEC_LO : SIReg <"EXEC LO", 126>;
|
||||
def EXEC_HI : SIReg <"EXEC HI", 127>;
|
||||
def EXEC : SI_64<"EXEC", [EXEC_LO, EXEC_HI], 126>;
|
||||
def SCC : SIReg<"SCC", 253>;
|
||||
def SREG_LIT_0 : SIReg <"S LIT 0", 128>;
|
||||
def SI_LITERAL_CONSTANT : SIReg<"LITERAL CONSTANT", 255>;
|
||||
def M0 : SIReg <"M0", 124>;
|
||||
|
||||
//Interpolation registers
|
||||
@ -136,7 +134,7 @@ def VGPR_512 : RegisterTuples<[sub0, sub1, sub2, sub3, sub4, sub5, sub6, sub7,
|
||||
|
||||
// Register class for all scalar registers (SGPRs + Special Registers)
|
||||
def SReg_32 : RegisterClass<"AMDGPU", [f32, i32], 32,
|
||||
(add SGPR_32, SREG_LIT_0, M0, EXEC_LO, EXEC_HI)
|
||||
(add SGPR_32, M0, EXEC_LO, EXEC_HI)
|
||||
>;
|
||||
|
||||
def SReg_64 : RegisterClass<"AMDGPU", [i64], 64, (add SGPR_64, VCC, EXEC)>;
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user