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[ELFYAML] Group ELF header falgs to target specific blocks. Handle flags

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which are corresponding to the current target read from the ELF file.

This fix cannot be tested until obj2yaml does not support ELF format.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@207905 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Simon Atanasyan 2014-05-03 11:39:50 +00:00
parent e6982bfe51
commit e26759bd66
1 changed files with 45 additions and 36 deletions
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81
lib/Object/ELFYAML.cpp
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@ -243,43 +243,52 @@ void ScalarEnumerationTraits<ELFYAML::ELF_ELFOSABI>::enumeration(
void ScalarBitSetTraits<ELFYAML::ELF_EF>::bitset(IO &IO,
ELFYAML::ELF_EF &Value) {
const auto *Object = static_cast<ELFYAML::Object *>(IO.getContext());
assert(Object && "The IO context is not initialized");
#define BCase(X) IO.bitSetCase(Value, #X, ELF::X);
BCase(EF_ARM_SOFT_FLOAT)
BCase(EF_ARM_VFP_FLOAT)
BCase(EF_ARM_EABI_UNKNOWN)
BCase(EF_ARM_EABI_VER1)
BCase(EF_ARM_EABI_VER2)
BCase(EF_ARM_EABI_VER3)
BCase(EF_ARM_EABI_VER4)
BCase(EF_ARM_EABI_VER5)
BCase(EF_ARM_EABIMASK)
BCase(EF_MIPS_NOREORDER)
BCase(EF_MIPS_PIC)
BCase(EF_MIPS_CPIC)
BCase(EF_MIPS_ABI2)
BCase(EF_MIPS_32BITMODE)
BCase(EF_MIPS_ABI_O32)
BCase(EF_MIPS_MICROMIPS)
BCase(EF_MIPS_ARCH_ASE_M16)
BCase(EF_MIPS_ARCH_1)
BCase(EF_MIPS_ARCH_2)
BCase(EF_MIPS_ARCH_3)
BCase(EF_MIPS_ARCH_4)
BCase(EF_MIPS_ARCH_5)
BCase(EF_MIPS_ARCH_32)
BCase(EF_MIPS_ARCH_64)
BCase(EF_MIPS_ARCH_32R2)
BCase(EF_MIPS_ARCH_64R2)
BCase(EF_MIPS_ARCH)
BCase(EF_HEXAGON_MACH_V2)
BCase(EF_HEXAGON_MACH_V3)
BCase(EF_HEXAGON_MACH_V4)
BCase(EF_HEXAGON_MACH_V5)
BCase(EF_HEXAGON_ISA_MACH)
BCase(EF_HEXAGON_ISA_V2)
BCase(EF_HEXAGON_ISA_V3)
BCase(EF_HEXAGON_ISA_V4)
BCase(EF_HEXAGON_ISA_V5)
switch (Object->Header.Machine) {
case ELF::EM_ARM:
BCase(EF_ARM_SOFT_FLOAT)
BCase(EF_ARM_VFP_FLOAT)
BCase(EF_ARM_EABI_UNKNOWN)
BCase(EF_ARM_EABI_VER1)
BCase(EF_ARM_EABI_VER2)
BCase(EF_ARM_EABI_VER3)
BCase(EF_ARM_EABI_VER4)
BCase(EF_ARM_EABI_VER5)
break;
case ELF::EM_MIPS:
BCase(EF_MIPS_NOREORDER)
BCase(EF_MIPS_PIC)
BCase(EF_MIPS_CPIC)
BCase(EF_MIPS_ABI2)
BCase(EF_MIPS_32BITMODE)
BCase(EF_MIPS_ABI_O32)
BCase(EF_MIPS_MICROMIPS)
BCase(EF_MIPS_ARCH_ASE_M16)
BCase(EF_MIPS_ARCH_1)
BCase(EF_MIPS_ARCH_2)
BCase(EF_MIPS_ARCH_3)
BCase(EF_MIPS_ARCH_4)
BCase(EF_MIPS_ARCH_5)
BCase(EF_MIPS_ARCH_32)
BCase(EF_MIPS_ARCH_64)
BCase(EF_MIPS_ARCH_32R2)
BCase(EF_MIPS_ARCH_64R2)
break;
case ELF::EM_HEXAGON:
BCase(EF_HEXAGON_MACH_V2)
BCase(EF_HEXAGON_MACH_V3)
BCase(EF_HEXAGON_MACH_V4)
BCase(EF_HEXAGON_MACH_V5)
BCase(EF_HEXAGON_ISA_V2)
BCase(EF_HEXAGON_ISA_V3)
BCase(EF_HEXAGON_ISA_V4)
BCase(EF_HEXAGON_ISA_V5)
break;
default:
llvm_unreachable("Unsupported architecture");
}
#undef BCase
}