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R600/SI: Fold fabs/fneg into src input modifier
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@208480 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1323,6 +1323,7 @@ SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
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// e64 version if available, -1 otherwise
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int OpcodeE64 = AMDGPU::getVOPe64(Opcode);
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const MCInstrDesc *DescE64 = OpcodeE64 == -1 ? nullptr : &TII->get(OpcodeE64);
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int InputModifiers[3] = {0};
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assert(!DescE64 || DescE64->getNumDefs() == NumDefs);
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@ -1399,7 +1400,10 @@ SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
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}
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}
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if (DescE64 && !Immediate) {
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if (Immediate)
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continue;
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if (DescE64) {
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// Test if it makes sense to switch to e64 encoding
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unsigned OtherRegClass = DescE64->OpInfo[Op].RegClass;
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@ -1418,6 +1422,31 @@ SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
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DescE64 = nullptr;
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}
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}
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if (!DescE64 && !Promote2e64)
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continue;
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if (!Operand.isMachineOpcode())
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continue;
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if (Operand.getMachineOpcode() == AMDGPU::FNEG_SI) {
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Ops.pop_back();
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Ops.push_back(Operand.getOperand(0));
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InputModifiers[i] = 1;
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Promote2e64 = true;
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if (!DescE64)
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continue;
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Desc = DescE64;
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DescE64 = 0;
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}
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else if (Operand.getMachineOpcode() == AMDGPU::FABS_SI) {
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Ops.pop_back();
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Ops.push_back(Operand.getOperand(0));
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InputModifiers[i] = 2;
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Promote2e64 = true;
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if (!DescE64)
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continue;
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Desc = DescE64;
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DescE64 = 0;
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}
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}
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if (Promote2e64) {
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@ -1425,7 +1454,7 @@ SDNode *SITargetLowering::foldOperands(MachineSDNode *Node,
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Ops.clear();
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for (unsigned i = 0; i < OldOps.size(); ++i) {
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// src_modifier
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Ops.push_back(DAG.getTargetConstant(0, MVT::i32));
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Ops.push_back(DAG.getTargetConstant(InputModifiers[i], MVT::i32));
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Ops.push_back(OldOps[i]);
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}
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// Add the modifier flags while promoting
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@ -49,6 +49,17 @@ entry:
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ret void
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}
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; SI-CHECK-LABEL: @fabs_fold
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; SI-CHECK-NOT: V_AND_B32_e32
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; SI-CHECK: V_MUL_F32_e64 v{{[0-9]+}}, s{{[0-9]+}}, |v{{[0-9]+}}|
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define void @fabs_fold(float addrspace(1)* %out, float %in0, float %in1) {
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entry:
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%0 = call float @fabs(float %in0)
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%1 = fmul float %0, %in1
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store float %1, float addrspace(1)* %out
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ret void
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}
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declare float @fabs(float ) readnone
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declare <2 x float> @llvm.fabs.v2f32(<2 x float> ) readnone
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declare <4 x float> @llvm.fabs.v4f32(<4 x float> ) readnone
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@ -59,3 +59,14 @@ entry:
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store float %1, float addrspace(1)* %out
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ret void
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}
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; SI-CHECK-LABEL: @fneg_fold
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; SI-CHECK-NOT: V_XOR_B32
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; SI-CHECK: V_MUL_F32_e64 v{{[0-9]+}}, s{{[0-9]+}}, -v{{[0-9]+}}
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define void @fneg_fold(float addrspace(1)* %out, float %in) {
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entry:
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%0 = fsub float -0.0, %in
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%1 = fmul float %0, %in
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store float %1, float addrspace(1)* %out
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ret void
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}
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