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[FastISel][AArch64] Optimize compare-and-branch for i1 to use 'tbz'.

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Minor enhancement to use 'tbz' for i1 compare-and-branch to get rid of an 'and'
instruction.

This fixes rdar://problem/18784953.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220712 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Juergen Ributzka 2014-10-27 19:46:23 +00:00
parent 7476f9c513
commit e2995ff88f
2 changed files with 5 additions and 2 deletions
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4
lib/Target/AArch64/AArch64FastISel.cpp
View File

@ -2132,6 +2132,10 @@ bool AArch64FastISel::emitCompareAndBranch(const BranchInst *BI) {
LHS = AndLHS;
}
}
if (VT == MVT::i1)
TestBit = 0;
IsCmpNE = Predicate == CmpInst::ICMP_NE;
} else if (Predicate == CmpInst::ICMP_SLT) {
if (!isa<Constant>(RHS))

3
test/CodeGen/AArch64/fast-isel-cbz.ll
View File

@ -2,8 +2,7 @@
define i32 @icmp_eq_i1(i1 %a) {
; CHECK-LABEL: icmp_eq_i1
; CHECK: and [[REG:w[0-9]+]], w0, #0x1
; CHECK: cbz [[REG]], {{LBB.+_2}}
; CHECK: tbz w0, #0, {{LBB.+_2}}
%1 = icmp eq i1 %a, 0
br i1 %1, label %bb1, label %bb2
bb2: