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[FastISel][AArch64] Optimize compare-and-branch for i1 to use 'tbz'.
Minor enhancement to use 'tbz' for i1 compare-and-branch to get rid of an 'and' instruction. This fixes rdar://problem/18784953. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@220712 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2132,6 +2132,10 @@ bool AArch64FastISel::emitCompareAndBranch(const BranchInst *BI) {
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LHS = AndLHS;
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}
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}
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if (VT == MVT::i1)
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TestBit = 0;
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IsCmpNE = Predicate == CmpInst::ICMP_NE;
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} else if (Predicate == CmpInst::ICMP_SLT) {
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if (!isa<Constant>(RHS))
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@ -2,8 +2,7 @@
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define i32 @icmp_eq_i1(i1 %a) {
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; CHECK-LABEL: icmp_eq_i1
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; CHECK: and [[REG:w[0-9]+]], w0, #0x1
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; CHECK: cbz [[REG]], {{LBB.+_2}}
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; CHECK: tbz w0, #0, {{LBB.+_2}}
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%1 = icmp eq i1 %a, 0
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br i1 %1, label %bb1, label %bb2
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bb2:
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