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ARM: add a couple more NEON predicates.
The fused multiply instructions were added in VFPv4 but are still NEON instructions, in particular they shouldn't be available on a Cortex-M4 not matter how floaty it is. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@193342 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -4301,19 +4301,19 @@ def : Pat<(v2i64 (int_arm_neon_vqsubs (v2i64 QPR:$src1),
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// Fused Vector Multiply-Accumulate and Fused Multiply-Subtract Operations.
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def VFMAfd : N3VDMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACD, "vfma", "f32",
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v2f32, fmul_su, fadd_mlx>,
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Requires<[HasVFP4,UseFusedMAC]>;
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Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
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def VFMAfq : N3VQMulOp<0, 0, 0b00, 0b1100, 1, IIC_VFMACQ, "vfma", "f32",
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v4f32, fmul_su, fadd_mlx>,
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Requires<[HasVFP4,UseFusedMAC]>;
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Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
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// Fused Vector Multiply Subtract (floating-point)
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def VFMSfd : N3VDMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACD, "vfms", "f32",
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v2f32, fmul_su, fsub_mlx>,
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Requires<[HasVFP4,UseFusedMAC]>;
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Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
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def VFMSfq : N3VQMulOp<0, 0, 0b10, 0b1100, 1, IIC_VFMACQ, "vfms", "f32",
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v4f32, fmul_su, fsub_mlx>,
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Requires<[HasVFP4,UseFusedMAC]>;
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Requires<[HasNEON,HasVFP4,UseFusedMAC]>;
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// Match @llvm.fma.* intrinsics
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def : Pat<(v2f32 (fma DPR:$Vn, DPR:$Vm, DPR:$src1)),
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@ -1,6 +1,8 @@
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@ RUN: llvm-mc < %s -triple armv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=ARM
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@ RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mattr=+neon,+vfp4 | FileCheck %s --check-prefix=THUMB
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@ RUN: llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mcpu=cortex-m4 | FileCheck %s --check-prefix=THUMB_V7EM
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@ RUN: not llvm-mc < %s -triple thumbv7-unknown-unknown -show-encoding -mcpu=cortex-m4 > %t 2> %t2
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@ RUN: FileCheck %s < %t --check-prefix=THUMB_V7EM
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@ RUN: FileCheck %s < %t2 --check-prefix=THUMB_V7EM-ERRORS
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@ ARM: vfma.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xe2,0xee]
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@ THUMB: vfma.f64 d16, d18, d17 @ encoding: [0xe2,0xee,0xa1,0x0b]
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@ -13,10 +15,14 @@ vfma.f32 s2, s4, s0
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@ ARM: vfma.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x42,0xf2]
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@ THUMB: vfma.f32 d16, d18, d17 @ encoding: [0x42,0xef,0xb1,0x0c]
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@ THUMB_V7EM-ERRORS: error: instruction requires: NEON
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@ THUMB_V7EM-ERRORS-NEXT: vfma.f32 d16, d18, d17
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vfma.f32 d16, d18, d17
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@ ARM: vfma.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x08,0xf2]
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@ THUMB: vfma.f32 q2, q4, q0 @ encoding: [0x08,0xef,0x50,0x4c]
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@ THUMB_V7EM-ERRORS: error: instruction requires: NEON
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@ THUMB_V7EM-ERRORS-NEXT: vfma.f32 q2, q4, q0
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vfma.f32 q2, q4, q0
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@ ARM: vfnma.f64 d16, d18, d17 @ encoding: [0xe1,0x0b,0xd2,0xee]
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@ -39,10 +45,14 @@ vfms.f32 s2, s4, s0
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@ ARM: vfms.f32 d16, d18, d17 @ encoding: [0xb1,0x0c,0x62,0xf2]
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@ THUMB: vfms.f32 d16, d18, d17 @ encoding: [0x62,0xef,0xb1,0x0c]
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@ THUMB_V7EM-ERRORS: error: instruction requires: NEON
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@ THUMB_V7EM-ERRORS-NEXT: vfms.f32 d16, d18, d17
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vfms.f32 d16, d18, d17
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@ ARM: vfms.f32 q2, q4, q0 @ encoding: [0x50,0x4c,0x28,0xf2]
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@ THUMB: vfms.f32 q2, q4, q0 @ encoding: [0x28,0xef,0x50,0x4c]
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@ THUMB_V7EM-ERRORS: error: instruction requires: NEON
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@ THUMB_V7EM-ERRORS-NEXT: vfms.f32 q2, q4, q0
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vfms.f32 q2, q4, q0
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@ ARM: vfnms.f64 d16, d18, d17 @ encoding: [0xa1,0x0b,0xd2,0xee]
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@ -51,4 +61,5 @@ vfnms.f64 d16, d18, d17
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@ ARM: vfnms.f32 s2, s4, s0 @ encoding: [0x00,0x1a,0x92,0xee]
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@ THUMB: vfnms.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x00,0x1a]
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@ THUMB_V7EM: vfnms.f32 s2, s4, s0 @ encoding: [0x92,0xee,0x00,0x1a]
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vfnms.f32 s2, s4, s0
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