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Add a `break' in the switch/case statement between the int/fp sections.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@14385 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1049,7 +1049,6 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
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///
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void ISel::visitReturnInst(ReturnInst &I) {
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Value *RetVal = I.getOperand(0);
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switch (getClassB(RetVal->getType())) {
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case cByte: // integral return values: extend or move into r3 and return
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case cShort:
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@ -1303,6 +1302,7 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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case cInt:
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// Integral results are in r3
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BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
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break;
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case cFP: // Floating-point return values live in f1
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BuildMI(BB, PPC32::FMR, 1, Ret.Reg).addReg(PPC32::F1);
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break;
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@ -1049,7 +1049,6 @@ void ISel::promote32(unsigned targetReg, const ValueRecord &VR) {
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///
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void ISel::visitReturnInst(ReturnInst &I) {
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Value *RetVal = I.getOperand(0);
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switch (getClassB(RetVal->getType())) {
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case cByte: // integral return values: extend or move into r3 and return
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case cShort:
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@ -1303,6 +1302,7 @@ void ISel::doCall(const ValueRecord &Ret, MachineInstr *CallMI,
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case cInt:
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// Integral results are in r3
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BuildMI(BB, PPC32::OR, 2, Ret.Reg).addReg(PPC32::R3).addReg(PPC32::R3);
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break;
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case cFP: // Floating-point return values live in f1
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BuildMI(BB, PPC32::FMR, 1, Ret.Reg).addReg(PPC32::F1);
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break;
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