6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2026-04-19 08:35:45 +00:00
Code Issues Projects Releases Wiki Activity

R600/SI: Use same names for corresponding MUBUF operands and encoding fields

Browse Source 
The code emitter knows how to encode operands whose name matches one of
the encoding fields.  If there is no match, the code emitter relies on
the order of the operand and field definitions to determine how operands
should be encoding.  Matching by order makes it easy to accidentally break
the instruction encodings, so we prefer to match by name.

Reviewed-by: Christian König <christian.koenig@amd.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178930 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2013-04-05 23:31:44 +00:00
parent 99eb040c02
commit e340b7728a
2 changed files with 26 additions and 26 deletions
Download Patch File Download Diff File Expand all files Collapse all files
lib/Target/R600/SIInstrFormats.td
+24 -24
View File
@@ -284,33 +284,33 @@ let Uses = [EXEC] in {
class MUBUF <bits<7> op, dag outs, dag ins, string asm, list<dag> pattern> :
Enc64<outs, ins, asm, pattern> {
bits<8> VDATA;
bits<12> OFFSET;
bits<1> OFFEN;
bits<1> IDXEN;
bits<1> GLC;
bits<1> ADDR64;
bits<1> LDS;
bits<8> VADDR;
bits<7> SRSRC;
bits<1> SLC;
bits<1> TFE;
bits<8> SOFFSET;
bits<12> offset;
bits<1> offen;
bits<1> idxen;
bits<1> glc;
bits<1> addr64;
bits<1> lds;
bits<8> vaddr;
bits<8> vdata;
bits<7> srsrc;
bits<1> slc;
bits<1> tfe;
bits<8> soffset;
let Inst{11-0} = OFFSET;
let Inst{12} = OFFEN;
let Inst{13} = IDXEN;
let Inst{14} = GLC;
let Inst{15} = ADDR64;
let Inst{16} = LDS;
let Inst{11-0} = offset;
let Inst{12} = offen;
let Inst{13} = idxen;
let Inst{14} = glc;
let Inst{15} = addr64;
let Inst{16} = lds;
let Inst{24-18} = op;
let Inst{31-26} = 0x38; //encoding
let Inst{39-32} = VADDR;
let Inst{47-40} = VDATA;
let Inst{52-48} = SRSRC{6-2};
let Inst{54} = SLC;
let Inst{55} = TFE;
let Inst{63-56} = SOFFSET;
let Inst{39-32} = vaddr;
let Inst{47-40} = vdata;
let Inst{52-48} = srsrc{6-2};
let Inst{54} = slc;
let Inst{55} = tfe;
let Inst{63-56} = soffset;
let VM_CNT = 1;
let EXP_CNT = 1;
lib/Target/R600/SIInstrInfo.td
+2 -2
View File
@@ -285,11 +285,11 @@ class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBU
class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF <
op,
(outs regClass:$dst),
(outs regClass:$vdata),
(ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64,
i1imm:$lds, VReg_32:$vaddr, SReg_128:$srsrc, i1imm:$slc,
i1imm:$tfe, SSrc_32:$soffset),
asm#" $dst, $offset, $offen, $idxen, $glc, $addr64, "
asm#" $vdata, $offset, $offen, $idxen, $glc, $addr64, "
#"$lds, $vaddr, $srsrc, $slc, $tfe, $soffset",
[]> {
let mayLoad = 1;