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Rename SHL, SHR, SAR, SHLD and SHLR instructions to make them
consistent with the rest and also pepare for the addition of their memory operand variants. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11902 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1776,17 +1776,17 @@ void ISel::emitShiftOperation(MachineBasicBlock *MBB,
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unsigned Class = getClass (ResultTy);
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static const unsigned ConstantOperand[][4] = {
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{ X86::SHRri8, X86::SHRri16, X86::SHRri32, X86::SHRDri32 }, // SHR
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{ X86::SARri8, X86::SARri16, X86::SARri32, X86::SHRDri32 }, // SAR
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{ X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDri32 }, // SHL
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{ X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDri32 }, // SAL = SHL
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{ X86::SHRri8, X86::SHRri16, X86::SHRri32, X86::SHRDrri32 }, // SHR
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{ X86::SARri8, X86::SARri16, X86::SARri32, X86::SHRDrri32 }, // SAR
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{ X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDrri32 }, // SHL
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{ X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDrri32 }, // SAL = SHL
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};
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static const unsigned NonConstantOperand[][4] = {
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{ X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR
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{ X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR
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{ X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL
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{ X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL
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{ X86::SHRrCL8, X86::SHRrCL16, X86::SHRrCL32 }, // SHR
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{ X86::SARrCL8, X86::SARrCL16, X86::SARrCL32 }, // SAR
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{ X86::SHLrCL8, X86::SHLrCL16, X86::SHLrCL32 }, // SHL
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{ X86::SHLrCL8, X86::SHLrCL16, X86::SHLrCL32 }, // SAL = SHL
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};
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// Longs, as usual, are handled specially...
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@ -1842,9 +1842,9 @@ void ISel::emitShiftOperation(MachineBasicBlock *MBB,
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unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
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if (isLeftShift) {
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// TmpReg2 = shld inHi, inLo
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BMI(MBB, IP, X86::SHLDrr32, 2, TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
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BMI(MBB, IP, X86::SHLDrrCL32,2,TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
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// TmpReg3 = shl inLo, CL
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BMI(MBB, IP, X86::SHLrr32, 1, TmpReg3).addReg(SrcReg);
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BMI(MBB, IP, X86::SHLrCL32, 1, TmpReg3).addReg(SrcReg);
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// Set the flags to indicate whether the shift was by more than 32 bits.
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BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
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@ -1857,9 +1857,9 @@ void ISel::emitShiftOperation(MachineBasicBlock *MBB,
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DestReg).addReg(TmpReg3).addReg(TmpReg);
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} else {
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// TmpReg2 = shrd inLo, inHi
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BMI(MBB, IP, X86::SHRDrr32, 2, TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
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BMI(MBB, IP, X86::SHRDrrCL32,2,TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
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// TmpReg3 = s[ah]r inHi, CL
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BMI(MBB, IP, isSigned ? X86::SARrr32 : X86::SHRrr32, 1, TmpReg3)
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BMI(MBB, IP, isSigned ? X86::SARrCL32 : X86::SHRrCL32, 1, TmpReg3)
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.addReg(SrcReg+1);
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// Set the flags to indicate whether the shift was by more than 32 bits.
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@ -1776,17 +1776,17 @@ void ISel::emitShiftOperation(MachineBasicBlock *MBB,
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unsigned Class = getClass (ResultTy);
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static const unsigned ConstantOperand[][4] = {
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{ X86::SHRri8, X86::SHRri16, X86::SHRri32, X86::SHRDri32 }, // SHR
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{ X86::SARri8, X86::SARri16, X86::SARri32, X86::SHRDri32 }, // SAR
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{ X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDri32 }, // SHL
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{ X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDri32 }, // SAL = SHL
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{ X86::SHRri8, X86::SHRri16, X86::SHRri32, X86::SHRDrri32 }, // SHR
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{ X86::SARri8, X86::SARri16, X86::SARri32, X86::SHRDrri32 }, // SAR
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{ X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDrri32 }, // SHL
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{ X86::SHLri8, X86::SHLri16, X86::SHLri32, X86::SHLDrri32 }, // SAL = SHL
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};
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static const unsigned NonConstantOperand[][4] = {
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{ X86::SHRrr8, X86::SHRrr16, X86::SHRrr32 }, // SHR
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{ X86::SARrr8, X86::SARrr16, X86::SARrr32 }, // SAR
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{ X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SHL
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{ X86::SHLrr8, X86::SHLrr16, X86::SHLrr32 }, // SAL = SHL
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{ X86::SHRrCL8, X86::SHRrCL16, X86::SHRrCL32 }, // SHR
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{ X86::SARrCL8, X86::SARrCL16, X86::SARrCL32 }, // SAR
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{ X86::SHLrCL8, X86::SHLrCL16, X86::SHLrCL32 }, // SHL
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{ X86::SHLrCL8, X86::SHLrCL16, X86::SHLrCL32 }, // SAL = SHL
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};
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// Longs, as usual, are handled specially...
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@ -1842,9 +1842,9 @@ void ISel::emitShiftOperation(MachineBasicBlock *MBB,
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unsigned TmpReg3 = makeAnotherReg(Type::IntTy);
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if (isLeftShift) {
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// TmpReg2 = shld inHi, inLo
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BMI(MBB, IP, X86::SHLDrr32, 2, TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
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BMI(MBB, IP, X86::SHLDrrCL32,2,TmpReg2).addReg(SrcReg+1).addReg(SrcReg);
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// TmpReg3 = shl inLo, CL
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BMI(MBB, IP, X86::SHLrr32, 1, TmpReg3).addReg(SrcReg);
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BMI(MBB, IP, X86::SHLrCL32, 1, TmpReg3).addReg(SrcReg);
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// Set the flags to indicate whether the shift was by more than 32 bits.
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BMI(MBB, IP, X86::TESTri8, 2).addReg(X86::CL).addZImm(32);
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@ -1857,9 +1857,9 @@ void ISel::emitShiftOperation(MachineBasicBlock *MBB,
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DestReg).addReg(TmpReg3).addReg(TmpReg);
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} else {
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// TmpReg2 = shrd inLo, inHi
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BMI(MBB, IP, X86::SHRDrr32, 2, TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
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BMI(MBB, IP, X86::SHRDrrCL32,2,TmpReg2).addReg(SrcReg).addReg(SrcReg+1);
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// TmpReg3 = s[ah]r inHi, CL
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BMI(MBB, IP, isSigned ? X86::SARrr32 : X86::SHRrr32, 1, TmpReg3)
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BMI(MBB, IP, isSigned ? X86::SARrCL32 : X86::SHRrCL32, 1, TmpReg3)
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.addReg(SrcReg+1);
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// Set the flags to indicate whether the shift was by more than 32 bits.
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@ -452,29 +452,32 @@ def TESTmi32 : X86Inst<"test", 0xF7, MRMS0m , Arg32>; // flags = [me
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// Shift instructions
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class UsesCL { list<Register> Uses = [CL]; bit printImplicitUses = 1; }
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def SHLrr8 : I2A8 <"shl", 0xD2, MRMS4r > , UsesCL; // R8 <<= cl
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def SHLrr16 : I2A8 <"shl", 0xD3, MRMS4r >, OpSize, UsesCL; // R16 <<= cl
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def SHLrr32 : I2A8 <"shl", 0xD3, MRMS4r > , UsesCL; // R32 <<= cl
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def SHLrCL8 : I2A8 <"shl", 0xD2, MRMS4r > , UsesCL; // R8 <<= cl
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def SHLrCL16 : I2A8 <"shl", 0xD3, MRMS4r >, OpSize, UsesCL; // R16 <<= cl
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def SHLrCL32 : I2A8 <"shl", 0xD3, MRMS4r > , UsesCL; // R32 <<= cl
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def SHLri8 : I2A8 <"shl", 0xC0, MRMS4r >; // R8 <<= imm8
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def SHLri16 : I2A8 <"shl", 0xC1, MRMS4r >, OpSize; // R16 <<= imm16
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def SHLri32 : I2A8 <"shl", 0xC1, MRMS4r >; // R32 <<= imm32
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def SHRrr8 : I2A8 <"shr", 0xD2, MRMS5r > , UsesCL; // R8 >>= cl
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def SHRrr16 : I2A8 <"shr", 0xD3, MRMS5r >, OpSize, UsesCL; // R16 >>= cl
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def SHRrr32 : I2A8 <"shr", 0xD3, MRMS5r > , UsesCL; // R32 >>= cl
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def SHRrCL8 : I2A8 <"shr", 0xD2, MRMS5r > , UsesCL; // R8 >>= cl
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def SHRrCL16 : I2A8 <"shr", 0xD3, MRMS5r >, OpSize, UsesCL; // R16 >>= cl
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def SHRrCL32 : I2A8 <"shr", 0xD3, MRMS5r > , UsesCL; // R32 >>= cl
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def SHRri8 : I2A8 <"shr", 0xC0, MRMS5r >; // R8 >>= imm8
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def SHRri16 : I2A8 <"shr", 0xC1, MRMS5r >, OpSize; // R16 >>= imm16
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def SHRri32 : I2A8 <"shr", 0xC1, MRMS5r >; // R32 >>= imm32
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def SARrr8 : I2A8 <"sar", 0xD2, MRMS7r > , UsesCL; // R8 >>>= cl
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def SARrr16 : I2A8 <"sar", 0xD3, MRMS7r >, OpSize, UsesCL; // R16 >>>= cl
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def SARrr32 : I2A8 <"sar", 0xD3, MRMS7r > , UsesCL; // R32 >>>= cl
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def SARrCL8 : I2A8 <"sar", 0xD2, MRMS7r > , UsesCL; // R8 >>>= cl
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def SARrCL16 : I2A8 <"sar", 0xD3, MRMS7r >, OpSize, UsesCL; // R16 >>>= cl
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def SARrCL32 : I2A8 <"sar", 0xD3, MRMS7r > , UsesCL; // R32 >>>= cl
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def SARri8 : I2A8 <"sar", 0xC0, MRMS7r >; // R8 >>>= imm8
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def SARri16 : I2A8 <"sar", 0xC1, MRMS7r >, OpSize; // R16 >>>= imm16
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def SARri32 : I2A8 <"sar", 0xC1, MRMS7r >; // R32 >>>= imm32
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def SHLDrr32 : I2A8 <"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl
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def SHLDri32 : I2A8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8
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def SHRDrr32 : I2A8 <"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl
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def SHRDri32 : I2A8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8
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def SHLDrrCL32 : I2A8 <"shld", 0xA5, MRMDestReg>, TB, UsesCL; // R32 <<= R32,R32 cl
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def SHLDrri32 : I2A8 <"shld", 0xA4, MRMDestReg>, TB; // R32 <<= R32,R32 imm8
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def SHRDrrCL32 : I2A8 <"shrd", 0xAD, MRMDestReg>, TB, UsesCL; // R32 >>= R32,R32 cl
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def SHRDrri32 : I2A8 <"shrd", 0xAC, MRMDestReg>, TB; // R32 >>= R32,R32 imm8
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// Condition code ops, incl. set if equal/not equal/...
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def SAHF : X86Inst<"sahf" , 0x9E, RawFrm, Arg8>, Imp<[AH],[]>; // flags = AH
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