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ARM: rename addrmode7 to addr_offset_none.
Use a more descriptive name so the code is more self-documenting. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@136704 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -726,12 +726,10 @@ def addrmodepc : Operand<i32>,
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let MIOperandInfo = (ops GPR, i32imm);
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}
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// addrmode7 := reg
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// Used by load/store exclusive instructions. Useful to enable right assembly
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// parsing and printing. Not used for any codegen matching.
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// addr_offset_none := reg
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//
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def MemMode7AsmOperand : AsmOperandClass { let Name = "MemMode7"; }
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def addrmode7 : Operand<i32> {
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def addr_offset_none : Operand<i32> {
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let PrintMethod = "printAddrMode7Operand";
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let MIOperandInfo = (ops GPR);
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let ParserMatchClass = MemMode7AsmOperand;
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@ -3753,29 +3751,30 @@ let usesCustomInserter = 1 in {
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}
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let mayLoad = 1 in {
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def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
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def LDREXB : AIldrex<0b10, (outs GPR:$Rt), (ins addr_offset_none:$addr),
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NoItinerary,
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"ldrexb", "\t$Rt, $addr", []>;
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def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
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def LDREXH : AIldrex<0b11, (outs GPR:$Rt), (ins addr_offset_none:$addr), NoItinerary,
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"ldrexh", "\t$Rt, $addr", []>;
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def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addrmode7:$addr), NoItinerary,
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def LDREX : AIldrex<0b00, (outs GPR:$Rt), (ins addr_offset_none:$addr), NoItinerary,
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"ldrex", "\t$Rt, $addr", []>;
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let hasExtraDefRegAllocReq = 1 in
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def LDREXD : AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2), (ins addrmode7:$addr),
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def LDREXD: AIldrex<0b01, (outs GPR:$Rt, GPR:$Rt2),(ins addr_offset_none:$addr),
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NoItinerary, "ldrexd", "\t$Rt, $Rt2, $addr", []>;
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}
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let mayStore = 1, Constraints = "@earlyclobber $Rd" in {
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def STREXB : AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
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def STREXB: AIstrex<0b10, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
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NoItinerary, "strexb", "\t$Rd, $Rt, $addr", []>;
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def STREXH : AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
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def STREXH: AIstrex<0b11, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
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NoItinerary, "strexh", "\t$Rd, $Rt, $addr", []>;
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def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addrmode7:$addr),
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def STREX : AIstrex<0b00, (outs GPR:$Rd), (ins GPR:$Rt, addr_offset_none:$addr),
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NoItinerary, "strex", "\t$Rd, $Rt, $addr", []>;
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}
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let hasExtraSrcRegAllocReq = 1, Constraints = "@earlyclobber $Rd" in
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def STREXD : AIstrex<0b01, (outs GPR:$Rd),
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(ins GPR:$Rt, GPR:$Rt2, addrmode7:$addr),
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(ins GPR:$Rt, GPR:$Rt2, addr_offset_none:$addr),
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NoItinerary, "strexd", "\t$Rd, $Rt, $Rt2, $addr", []>;
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// Clear-Exclusive is for disassembly only.
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@ -3787,8 +3786,10 @@ def CLREX : AXI<(outs), (ins), MiscFrm, NoItinerary, "clrex",
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// SWP/SWPB are deprecated in V6/V7.
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let mayLoad = 1, mayStore = 1 in {
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def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addrmode7:$addr), "swp", []>;
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def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addrmode7:$addr), "swpb", []>;
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def SWP : AIswp<0, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
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"swp", []>;
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def SWPB: AIswp<1, (outs GPR:$Rt), (ins GPR:$Rt2, addr_offset_none:$addr),
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"swpb", []>;
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}
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//===----------------------------------------------------------------------===//
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@ -651,7 +651,7 @@ static int ARMFlagFromOpName(LiteralConstantEmitter *type,
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MISC("addrmode6dup", "kOperandTypeARMAddrMode6"); // R, R, I, I
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MISC("addrmode6oneL32", "kOperandTypeARMAddrMode6"); // R, R, I, I
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MISC("addrmodepc", "kOperandTypeARMAddrModePC"); // R, I
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MISC("addrmode7", "kOperandTypeARMAddrMode7"); // R
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MISC("addr_offset_none", "kOperandTypeARMAddrMode7"); // R
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MISC("reglist", "kOperandTypeARMRegisterList"); // I, R, ...
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MISC("dpr_reglist", "kOperandTypeARMDPRRegisterList"); // I, R, ...
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MISC("spr_reglist", "kOperandTypeARMSPRRegisterList"); // I, R, ...
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