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fix some warnings in release-asserts mode.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@67738 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2009-03-26 05:28:26 +00:00
parent d4015074e4
commit e3a85838da
1 changed files with 19 additions and 20 deletions

39
lib/Target/Mips/MipsInstrInfo.cpp

@ -182,8 +182,7 @@ copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
void MipsInstrInfo::
storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
unsigned SrcReg, bool isKill, int FI,
const TargetRegisterClass *RC) const
{
const TargetRegisterClass *RC) const {
unsigned Opc;
DebugLoc DL = DebugLoc::getUnknownLoc();
@ -193,11 +192,11 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
Opc = Mips::SW;
else if (RC == Mips::FGR32RegisterClass)
Opc = Mips::SWC1;
else if (RC == Mips::AFGR64RegisterClass)
else {
assert(RC == Mips::AFGR64RegisterClass);
Opc = Mips::SDC1;
else
assert(0 && "Can't store this register to stack slot");
}
BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, false, false, isKill)
.addImm(0).addFrameIndex(FI);
}
@ -211,11 +210,11 @@ void MipsInstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
Opc = Mips::SW;
else if (RC == Mips::FGR32RegisterClass)
Opc = Mips::SWC1;
else if (RC == Mips::AFGR64RegisterClass)
else {
assert(RC == Mips::AFGR64RegisterClass);
Opc = Mips::SDC1;
else
assert(0 && "Can't store this register");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc))
.addReg(SrcReg, false, false, isKill);
@ -235,11 +234,11 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
Opc = Mips::LW;
else if (RC == Mips::FGR32RegisterClass)
Opc = Mips::LWC1;
else if (RC == Mips::AFGR64RegisterClass)
else {
assert(RC == Mips::AFGR64RegisterClass);
Opc = Mips::LDC1;
else
assert(0 && "Can't load this register from stack slot");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
if (I != MBB.end()) DL = I->getDebugLoc();
BuildMI(MBB, I, DL, get(Opc), DestReg).addImm(0).addFrameIndex(FI);
@ -254,10 +253,10 @@ void MipsInstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
Opc = Mips::LW;
else if (RC == Mips::FGR32RegisterClass)
Opc = Mips::LWC1;
else if (RC == Mips::AFGR64RegisterClass)
else {
assert(RC == Mips::AFGR64RegisterClass);
Opc = Mips::LDC1;
else
assert(0 && "Can't load this register");
}
DebugLoc DL = DebugLoc::getUnknownLoc();
MachineInstrBuilder MIB = BuildMI(MF, DL, get(Opc), DestReg);
@ -307,10 +306,10 @@ foldMemoryOperandImpl(MachineFunction &MF,
if (RC == Mips::FGR32RegisterClass) {
LoadOpc = Mips::LWC1; StoreOpc = Mips::SWC1;
} else if (RC == Mips::AFGR64RegisterClass) {
} else {
assert(RC == Mips::AFGR64RegisterClass);
LoadOpc = Mips::LDC1; StoreOpc = Mips::SDC1;
} else
assert(0 && "foldMemoryOperandImpl register unknown");
}
if (Ops[0] == 0) { // COPY -> STORE
unsigned SrcReg = MI->getOperand(1).getReg();