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Basic implementation of SSEDomainFix pass.
Cross-block inference is primitive and wrong, but the pass is working otherwise. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@99848 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jakob Stoklund Olesen
parent
bfde644e8a
commit
e4b94b4efb
@ -29,12 +29,108 @@
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using namespace llvm;
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namespace {
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/// Allocate objects from a pool, allow objects to be recycled, and provide a
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/// way of deleting everything.
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template<typename T, unsigned PageSize = 64>
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class PoolAllocator {
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std::vector<T*> Pages, Avail;
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public:
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~PoolAllocator() { Clear(); }
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T* Alloc() {
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if (Avail.empty()) {
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T *p = new T[PageSize];
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Pages.push_back(p);
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Avail.reserve(PageSize);
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for (unsigned n = 0; n != PageSize; ++n)
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Avail.push_back(p+n);
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}
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T *p = Avail.back();
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Avail.pop_back();
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return p;
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}
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// Allow object to be reallocated. It won't be reconstructed.
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void Recycle(T *p) {
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p->clear();
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Avail.push_back(p);
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}
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// Destroy all objects, make sure there are no external pointers to them.
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void Clear() {
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Avail.clear();
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while (!Pages.empty()) {
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delete[] Pages.back();
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Pages.pop_back();
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}
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}
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};
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/// A DomainValue is a bit like LiveIntervals' ValNo, but it laso keeps track
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/// of execution domains.
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///
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/// An open DomainValue represents a set of instructions that can still switch
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/// execution domain. Multiple registers may refer to the same open
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/// DomainValue - they will eventually be collapsed to the same execution
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/// domain.
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///
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/// A collapsed DomainValue represents a single register that has been forced
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/// into one of more execution domains. There is a separate collapsed
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/// DomainValue for each register, but it may contain multiple execution
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/// domains. A register value is initially created in a single execution
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/// domain, but if we were forced to pay the penalty of a domain crossing, we
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/// keep track of the fact the the register is now available in multiple
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/// domains.
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struct DomainValue {
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// Basic reference counting.
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unsigned Refs;
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// Available domains. For an open DomainValue, it is the still possible
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// domains for collapsing. For a collapsed DomainValue it is the domains where
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// the register is available for free.
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unsigned Mask;
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// Position of the last defining instruction.
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unsigned Dist;
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// Twiddleable instructions using or defining these registers.
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SmallVector<MachineInstr*, 8> Instrs;
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// Collapsed DomainValue have no instructions to twiddle - it simply keeps
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// track of the domains where the registers are already available.
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bool collapsed() const { return Instrs.empty(); }
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// Is any domain in mask available?
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bool compat(unsigned mask) const {
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return Mask & mask;
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}
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// Mark domain as available
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void add(unsigned domain) {
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Mask |= 1u << domain;
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}
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DomainValue() { clear(); }
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void clear() {
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Refs = Mask = Dist = 0;
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Instrs.clear();
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}
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};
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class SSEDomainFixPass : public MachineFunctionPass {
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static char ID;
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const X86InstrInfo *TII;
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PoolAllocator<DomainValue> Pool;
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MachineFunction *MF;
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const X86InstrInfo *TII;
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const TargetRegisterInfo *TRI;
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MachineBasicBlock *MBB;
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bool hasLiveRegs;
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DomainValue *LiveRegs[16];
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public:
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SSEDomainFixPass() : MachineFunctionPass(&ID) {}
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@ -50,47 +146,288 @@ public:
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}
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private:
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// Register mapping.
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int RegIndex(unsigned Reg);
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// LiveRegs manipulations.
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void SetLiveReg(int rx, DomainValue *DV);
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void Kill(int rx);
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void Force(int rx, unsigned domain);
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void Collapse(DomainValue *dv, unsigned domain);
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bool Merge(DomainValue *A, DomainValue *B);
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void enterBasicBlock(MachineBasicBlock *MBB);
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void visitGenericInstr(MachineInstr*);
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void visitSoftInstr(MachineInstr*, unsigned mask);
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void visitHardInstr(MachineInstr*, unsigned domain);
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};
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}
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char SSEDomainFixPass::ID = 0;
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/// Translate TRI register number to an index into our smaller tables of
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/// interesting registers. Return -1 for boring registers.
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int SSEDomainFixPass::RegIndex(unsigned reg) {
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// Registers are sorted lexicographically.
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// We just need them to be consecutive, ordering doesn't matter.
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assert(X86::XMM9 == X86::XMM0+15 && "Unexpected sort");
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reg -= X86::XMM0;
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return reg < 16 ? reg : -1;
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}
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/// Set LiveRegs[rx] = dv, updating reference counts.
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void SSEDomainFixPass::SetLiveReg(int rx, DomainValue *dv) {
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if (LiveRegs[rx] == dv)
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return;
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if (LiveRegs[rx]) {
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assert(LiveRegs[rx]->Refs && "Bad refcount");
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if (--LiveRegs[rx]->Refs == 0) Pool.Recycle(LiveRegs[rx]);
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}
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LiveRegs[rx] = dv;
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if (dv) ++dv->Refs;
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}
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// Kill register rx, recycle or collapse any DomainValue.
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void SSEDomainFixPass::Kill(int rx) {
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if (!LiveRegs[rx]) return;
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// Before killing the last reference to an open DomainValue, collapse it to
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// the first available domain.
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if (LiveRegs[rx]->Refs == 1 && !LiveRegs[rx]->collapsed())
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Collapse(LiveRegs[rx], CountTrailingZeros_32(LiveRegs[rx]->Mask));
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else
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SetLiveReg(rx, 0);
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}
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/// Force register rx into domain.
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void SSEDomainFixPass::Force(int rx, unsigned domain) {
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hasLiveRegs = true;
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if (DomainValue *dv = LiveRegs[rx]) {
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if (dv->collapsed())
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dv->add(domain);
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else
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Collapse(dv, domain);
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} else {
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// Set up basic collapsed DomainValue
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DomainValue *dv = Pool.Alloc();
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dv->add(domain);
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SetLiveReg(rx, dv);
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}
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}
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/// Collapse open DomainValue into given domain. If there are multiple
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/// registers using dv, they each get a unique collapsed DomainValue.
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void SSEDomainFixPass::Collapse(DomainValue *dv, unsigned domain) {
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assert(dv->compat(1u << domain) && "Cannot collapse");
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// Collapse all the instructions.
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while (!dv->Instrs.empty()) {
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MachineInstr *mi = dv->Instrs.back();
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TII->SetSSEDomain(mi, domain);
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dv->Instrs.pop_back();
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}
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dv->Mask = 1u << domain;
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// If there are multiple users, give them new, unique DomainValues.
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if (dv->Refs > 1) {
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for (unsigned rx=0, e = array_lengthof(LiveRegs); rx != e; ++rx)
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if (LiveRegs[rx] == dv) {
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DomainValue *dv2 = Pool.Alloc();
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dv2->add(domain);
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SetLiveReg(rx, dv2);
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}
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Pool.Recycle(dv);
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}
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}
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/// Merge - All instructions and registers in B are moved to A, and B is
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/// released.
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bool SSEDomainFixPass::Merge(DomainValue *A, DomainValue *B) {
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assert(!A->collapsed() && "Cannot merge into collapsed");
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assert(!B->collapsed() && "Cannot merge from collapsed");
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if (!A->compat(B->Mask))
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return false;
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A->Mask &= B->Mask;
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A->Dist = std::max(A->Dist, B->Dist);
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A->Instrs.append(B->Instrs.begin(), B->Instrs.end());
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for (unsigned rx=0, e = array_lengthof(LiveRegs); rx != e; ++rx)
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if (LiveRegs[rx] == B)
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SetLiveReg(rx, A);
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return true;
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}
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void SSEDomainFixPass::enterBasicBlock(MachineBasicBlock *mbb) {
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MBB = mbb;
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DEBUG(dbgs() << "Entering MBB " << MBB->getName() << "\n");
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}
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// A hard instruction only works in one domain. All input registers will be
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// forced into that domain.
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void SSEDomainFixPass::visitHardInstr(MachineInstr *mi, unsigned domain) {
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// Collapse all uses.
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for (unsigned i = mi->getDesc().getNumDefs(),
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e = mi->getDesc().getNumOperands(); i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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if (!mo.isReg()) continue;
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int rx = RegIndex(mo.getReg());
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if (rx < 0) continue;
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Force(rx, domain);
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}
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// Kill all defs and force them.
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for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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if (!mo.isReg()) continue;
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int rx = RegIndex(mo.getReg());
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if (rx < 0) continue;
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Kill(rx);
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Force(rx, domain);
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}
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}
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// A soft instruction can be changed to work in other domains given by mask.
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void SSEDomainFixPass::visitSoftInstr(MachineInstr *mi, unsigned mask) {
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// Scan the explicit use operands for incoming domains.
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unsigned collmask = mask;
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SmallVector<int, 4> used;
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for (unsigned i = mi->getDesc().getNumDefs(),
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e = mi->getDesc().getNumOperands(); i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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if (!mo.isReg()) continue;
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int rx = RegIndex(mo.getReg());
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if (rx < 0) continue;
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if (DomainValue *dv = LiveRegs[rx]) {
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// Is it possible to use this collapsed register for free?
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if (dv->collapsed()) {
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if (unsigned m = collmask & dv->Mask)
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collmask = m;
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} else if (dv->compat(collmask))
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used.push_back(rx);
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else
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Kill(rx);
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}
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}
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// If the collapsed operands force a single domain, propagate the collapse.
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if (isPowerOf2_32(collmask)) {
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unsigned domain = CountTrailingZeros_32(collmask);
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TII->SetSSEDomain(mi, domain);
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visitHardInstr(mi, domain);
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return;
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}
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// Kill off any remaining uses that don't match collmask, and build a list of
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// incoming DomainValue that we want to merge.
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SmallVector<DomainValue*,4> doms;
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for (SmallVector<int, 4>::iterator i=used.begin(), e=used.end(); i!=e; ++i) {
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int rx = *i;
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DomainValue *dv = LiveRegs[rx];
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// This useless DomainValue could have been missed above
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if (!dv->compat(collmask)) {
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Kill(*i);
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continue;
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}
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// sorted, uniqued insert.
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bool inserted = false;
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for (SmallVector<DomainValue*,4>::iterator i = doms.begin(), e = doms.end();
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i != e && !inserted; ++i) {
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if (dv == *i)
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inserted = true;
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else if (dv->Dist < (*i)->Dist) {
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inserted = true;
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doms.insert(i, dv);
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}
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}
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if (!inserted)
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doms.push_back(dv);
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}
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// doms are now sorted in order of appearance. Try to merge them all, giving
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// priority to the latest ones.
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DomainValue *dv = 0;
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while (!doms.empty()) {
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if (!dv)
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dv = doms.back();
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else if (!Merge(dv, doms.back()))
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for (SmallVector<int,4>::iterator i=used.begin(), e=used.end(); i!=e; ++i)
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if (LiveRegs[*i] == doms.back())
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Kill(*i);
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doms.pop_back();
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}
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// dv is the DomainValue we are going to use for this instruction.
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if (!dv)
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dv = Pool.Alloc();
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dv->Mask = collmask;
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dv->Instrs.push_back(mi);
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// Finally set all defs and non-collapsed uses to dv.
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for (unsigned i = 0, e = mi->getDesc().getNumOperands(); i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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if (!mo.isReg()) continue;
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int rx = RegIndex(mo.getReg());
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if (rx < 0) continue;
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if (!LiveRegs[rx] || (mo.isDef() && LiveRegs[rx]!=dv)) {
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Kill(rx);
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SetLiveReg(rx, dv);
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}
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}
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}
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void SSEDomainFixPass::visitGenericInstr(MachineInstr *mi) {
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// Process explicit defs, kill any XMM registers redefined
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for (unsigned i = 0, e = mi->getDesc().getNumDefs(); i != e; ++i) {
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MachineOperand &mo = mi->getOperand(i);
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if (!mo.isReg()) continue;
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int rx = RegIndex(mo.getReg());
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if (rx < 0) continue;
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Kill(rx);
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}
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}
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bool SSEDomainFixPass::runOnMachineFunction(MachineFunction &mf) {
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MF = &mf;
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TII = static_cast<const X86InstrInfo*>(MF->getTarget().getInstrInfo());
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TRI = MF->getTarget().getRegisterInfo();
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MBB = 0;
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hasLiveRegs = false;
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for (unsigned i=0, e = array_lengthof(LiveRegs); i != e; ++i)
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LiveRegs[i] = 0;
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// If no XMM registers are used in the function, we can skip it completely.
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bool XMMIsUsed = false;
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bool anyregs = false;
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for (TargetRegisterClass::const_iterator I = X86::VR128RegClass.begin(),
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E = X86::VR128RegClass.end(); I != E; ++I)
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if (MF->getRegInfo().isPhysRegUsed(*I)) {
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XMMIsUsed = true;
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anyregs = true;
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break;
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}
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if (!XMMIsUsed) return false;
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if (!anyregs) return false;
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MachineBasicBlock *Entry = MF->begin();
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SmallPtrSet<MachineBasicBlock*, 16> Visited;
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for (df_ext_iterator<MachineBasicBlock*,
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SmallPtrSet<MachineBasicBlock*, 16> >
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for (df_ext_iterator<MachineBasicBlock*, SmallPtrSet<MachineBasicBlock*, 16> >
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DFI = df_ext_begin(Entry, Visited), DFE = df_ext_end(Entry, Visited);
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DFI != DFE; ++DFI) {
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DFI != DFE; ++DFI) {
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enterBasicBlock(*DFI);
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for (MachineBasicBlock::iterator I = MBB->begin(), E = MBB->end(); I != E;
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++I) {
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MachineInstr *MI = I;
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const unsigned *equiv = 0;
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X86InstrInfo::SSEDomain domain = TII->GetSSEDomain(MI, equiv);
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(void) domain;
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DEBUG(dbgs() << "-isd"[domain] << (equiv ? "* " : " ") << *MI);
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MachineInstr *mi = I;
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if (mi->isDebugValue()) continue;
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std::pair<uint16_t, uint16_t> domp = TII->GetSSEDomain(mi);
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if (domp.first)
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if (domp.second)
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visitSoftInstr(mi, domp.second);
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else
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visitHardInstr(mi, domp.first);
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else if (hasLiveRegs)
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visitGenericInstr(mi);
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}
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}
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Pool.Clear();
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return false;
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}
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@ -3659,45 +3659,49 @@ unsigned X86InstrInfo::getGlobalBaseReg(MachineFunction *MF) const {
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return GlobalBaseReg;
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}
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X86InstrInfo::SSEDomain X86InstrInfo::GetSSEDomain(const MachineInstr *MI,
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const unsigned *&equiv) const {
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// These are the replaceable SSE instructions. Some of these have Int variants
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// that we don't include here. We don't want to replace instructions selected
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// by intrinsics.
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static const unsigned ReplaceableInstrs[][3] = {
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//PackedInt PackedSingle PackedDouble
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{ X86::MOVDQAmr, X86::MOVAPSmr, X86::MOVAPDmr },
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{ X86::MOVDQArm, X86::MOVAPSrm, X86::MOVAPDrm },
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{ X86::MOVDQArr, X86::MOVAPSrr, X86::MOVAPDrr },
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{ X86::MOVDQUmr, X86::MOVUPSmr, X86::MOVUPDmr },
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{ X86::MOVDQUrm, X86::MOVUPSrm, X86::MOVUPDrm },
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{ X86::MOVNTDQmr, X86::MOVNTPSmr, X86::MOVNTPDmr },
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{ X86::PANDNrm, X86::ANDNPSrm, X86::ANDNPDrm },
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{ X86::PANDNrr, X86::ANDNPSrr, X86::ANDNPDrr },
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{ X86::PANDrm, X86::ANDPSrm, X86::ANDPDrm },
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{ X86::PANDrr, X86::ANDPSrr, X86::ANDPDrr },
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{ X86::PORrm, X86::ORPSrm, X86::ORPDrm },
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{ X86::PORrr, X86::ORPSrr, X86::ORPDrr },
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{ X86::PUNPCKHQDQrm, X86::UNPCKHPSrm, X86::UNPCKHPDrm },
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{ X86::PUNPCKHQDQrr, X86::UNPCKHPSrr, X86::UNPCKHPDrr },
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{ X86::PUNPCKLQDQrm, X86::UNPCKLPSrm, X86::UNPCKLPDrm },
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{ X86::PUNPCKLQDQrr, X86::UNPCKLPSrr, X86::UNPCKLPDrr },
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{ X86::PXORrm, X86::XORPSrm, X86::XORPDrm },
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{ X86::PXORrr, X86::XORPSrr, X86::XORPDrr },
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};
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// These are the replaceable SSE instructions. Some of these have Int variants
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// that we don't include here. We don't want to replace instructions selected
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// by intrinsics.
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static const unsigned ReplaceableInstrs[][3] = {
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//PackedInt PackedSingle PackedDouble
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{ X86::MOVDQAmr, X86::MOVAPSmr, X86::MOVAPDmr },
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{ X86::MOVDQArm, X86::MOVAPSrm, X86::MOVAPDrm },
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||||
{ X86::MOVDQArr, X86::MOVAPSrr, X86::MOVAPDrr },
|
||||
{ X86::MOVDQUmr, X86::MOVUPSmr, X86::MOVUPDmr },
|
||||
{ X86::MOVDQUrm, X86::MOVUPSrm, X86::MOVUPDrm },
|
||||
{ X86::MOVNTDQmr, X86::MOVNTPSmr, X86::MOVNTPDmr },
|
||||
{ X86::PANDNrm, X86::ANDNPSrm, X86::ANDNPDrm },
|
||||
{ X86::PANDNrr, X86::ANDNPSrr, X86::ANDNPDrr },
|
||||
{ X86::PANDrm, X86::ANDPSrm, X86::ANDPDrm },
|
||||
{ X86::PANDrr, X86::ANDPSrr, X86::ANDPDrr },
|
||||
{ X86::PORrm, X86::ORPSrm, X86::ORPDrm },
|
||||
{ X86::PORrr, X86::ORPSrr, X86::ORPDrr },
|
||||
{ X86::PXORrm, X86::XORPSrm, X86::XORPDrm },
|
||||
{ X86::PXORrr, X86::XORPSrr, X86::XORPDrr },
|
||||
};
|
||||
|
||||
const SSEDomain domain =
|
||||
SSEDomain((MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3);
|
||||
if (domain == NotSSEDomain)
|
||||
return domain;
|
||||
// FIXME: Some shuffle and unpack instructions have equivalents in different
|
||||
// domains, but they require a bit more work than just switching opcodes.
|
||||
|
||||
// Linear search FTW!
|
||||
const unsigned opc = MI->getOpcode();
|
||||
static const unsigned *lookup(unsigned opcode, unsigned domain) {
|
||||
for (unsigned i = 0, e = array_lengthof(ReplaceableInstrs); i != e; ++i)
|
||||
if (ReplaceableInstrs[i][domain-1] == opc) {
|
||||
equiv = ReplaceableInstrs[i];
|
||||
return domain;
|
||||
}
|
||||
equiv = 0;
|
||||
return domain;
|
||||
if (ReplaceableInstrs[i][domain-1] == opcode)
|
||||
return ReplaceableInstrs[i];
|
||||
return 0;
|
||||
}
|
||||
|
||||
std::pair<uint16_t, uint16_t>
|
||||
X86InstrInfo::GetSSEDomain(const MachineInstr *MI) const {
|
||||
uint16_t domain = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
|
||||
return std::make_pair(domain, domain != NotSSEDomain &&
|
||||
lookup(MI->getOpcode(), domain) ? 0xe : 0);
|
||||
}
|
||||
|
||||
void X86InstrInfo::SetSSEDomain(MachineInstr *MI, unsigned Domain) const {
|
||||
assert(Domain>0 && Domain<4 && "Invalid execution domain");
|
||||
uint16_t dom = (MI->getDesc().TSFlags >> X86II::SSEDomainShift) & 3;
|
||||
assert(dom && "Not an SSE instruction");
|
||||
const unsigned *table = lookup(MI->getOpcode(), dom);
|
||||
assert(table && "Cannot change domain");
|
||||
MI->setDesc(get(table[Domain-1]));
|
||||
}
|
||||
|
||||
@ -722,11 +722,12 @@ public:
|
||||
/// Some SSE instructions come in variants for three domains.
|
||||
enum SSEDomain { NotSSEDomain, PackedInt, PackedSingle, PackedDouble };
|
||||
|
||||
/// GetSSEDomain - Return the SSE execution domain of MI, or NotSSEDomain for
|
||||
/// unknown instructions. If the instruction has equivalents for other
|
||||
/// domains, equiv points to a list of opcodes for [PackedInt, PackedSingle,
|
||||
/// PackedDouble].
|
||||
SSEDomain GetSSEDomain(const MachineInstr *MI, const unsigned *&equiv) const;
|
||||
/// GetSSEDomain - Return the SSE execution domain of MI as the first element,
|
||||
/// and a bitmask of possible arguments to SetSSEDomain ase the second.
|
||||
std::pair<uint16_t, uint16_t> GetSSEDomain(const MachineInstr *MI) const;
|
||||
|
||||
/// SetSSEDomain - Set the SSEDomain of MI.
|
||||
void SetSSEDomain(MachineInstr *MI, unsigned Domain) const;
|
||||
|
||||
private:
|
||||
MachineInstr * convertToThreeAddressWithLEA(unsigned MIOpc,
|
||||
|
||||
Loading…
x
Reference in New Issue
Block a user