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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
Move some methods out of MachineInstr into MachineOperand
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28102 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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e3158308e0
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e53f4a055f
@ -234,7 +234,7 @@ public:
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extra.regNum = Reg;
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}
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void setImmedValue(int immVal) {
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void setImmedValue(int64_t immVal) {
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assert(isImmediate() && "Wrong MachineOperand mutator");
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contents.immedVal = immVal;
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}
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@ -245,6 +245,22 @@ public:
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"Wrong MachineOperand accessor");
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extra.offset = Offset;
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}
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/// ChangeToImmediate - Replace this operand with a new immediate operand of
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/// the specified value. If an operand is known to be an immediate already,
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/// the setImmedValue method should be used.
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void ChangeToImmediate(int64_t ImmVal) {
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opType = MO_Immediate;
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contents.immedVal = ImmVal;
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}
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/// ChangeToRegister - Replace this operand with a new register operand of
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/// the specified value. If an operand is known to be an register already,
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/// the setReg method should be used.
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void ChangeToRegister(unsigned Reg) {
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opType = MO_VirtualRegister;
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extra.regNum = Reg;
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}
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friend std::ostream& operator<<(std::ostream& os, const MachineOperand& mop);
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@ -436,7 +452,6 @@ public:
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//===--------------------------------------------------------------------===//
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// Accessors used to modify instructions in place.
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//
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// FIXME: Move this stuff to MachineOperand itself!
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/// setOpcode - Replace the opcode of the current instruction with a new one.
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///
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@ -448,14 +463,6 @@ public:
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void RemoveOperand(unsigned i) {
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operands.erase(operands.begin()+i);
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}
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// Access to set the operands when building the machine instruction
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//
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void SetMachineOperandConst(unsigned i,
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MachineOperand::MachineOperandType operandType,
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int intValue);
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void SetMachineOperandReg(unsigned i, int regNum);
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};
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//===----------------------------------------------------------------------===//
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@ -187,7 +187,7 @@ bool LiveIntervals::runOnMachineFunction(MachineFunction &fn) {
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MRegisterInfo::isVirtualRegister(mop.getReg())) {
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// replace register with representative register
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unsigned reg = rep(mop.getReg());
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mii->SetMachineOperandReg(i, reg);
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mii->getOperand(i).setReg(reg);
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LiveInterval &RegInt = getInterval(reg);
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RegInt.weight +=
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@ -263,7 +263,7 @@ addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
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if (NewRegLiveIn && mop.isUse()) {
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// We already emitted a reload of this value, reuse it for
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// subsequent operands.
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MI->SetMachineOperandReg(i, NewRegLiveIn);
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MI->getOperand(i).setReg(NewRegLiveIn);
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DEBUG(std::cerr << "\t\t\t\treused reload into reg" << NewRegLiveIn
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<< " for operand #" << i << '\n');
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} else if (MachineInstr* fmi = mri_->foldMemoryOperand(MI, i, slot)) {
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@ -300,7 +300,7 @@ addIntervalsForSpills(const LiveInterval &li, VirtRegMap &vrm, int slot) {
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// create a new register for this spill
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NewRegLiveIn = mf_->getSSARegMap()->createVirtualRegister(rc);
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MI->SetMachineOperandReg(i, NewRegLiveIn);
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MI->getOperand(i).setReg(NewRegLiveIn);
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vrm.grow();
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vrm.assignVirt2StackSlot(NewRegLiveIn, slot);
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LiveInterval& nI = getOrCreateInterval(NewRegLiveIn);
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@ -107,25 +107,6 @@ bool MachineInstr::OperandsComplete() const {
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return false;
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}
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void
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MachineInstr::SetMachineOperandConst(unsigned i,
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MachineOperand::MachineOperandType opTy,
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int intValue) {
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assert(i < getNumOperands());
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operands[i].opType = opTy;
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operands[i].contents.immedVal = intValue;
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operands[i].extra.regNum = -1;
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operands[i].flags = 0;
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}
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void MachineInstr::SetMachineOperandReg(unsigned i, int regNum) {
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assert(i < getNumOperands());
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operands[i].opType = MachineOperand::MO_VirtualRegister;
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operands[i].contents.GV = NULL;
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operands[i].extra.regNum = regNum;
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}
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void MachineInstr::dump() const {
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std::cerr << " " << *this;
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}
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@ -443,7 +443,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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// and return.
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if (unsigned PR = getVirt2PhysRegMapSlot(VirtReg)) {
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MarkPhysRegRecentlyUsed(PR); // Already have this value available!
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MI->SetMachineOperandReg(OpNum, PR); // Assign the input register
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MI->getOperand(OpNum).setReg(PR); // Assign the input register
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return MI;
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}
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@ -481,7 +481,7 @@ MachineInstr *RA::reloadVirtReg(MachineBasicBlock &MBB, MachineInstr *MI,
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++NumLoads; // Update statistics
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PhysRegsEverUsed[PhysReg] = true;
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MI->SetMachineOperandReg(OpNum, PhysReg); // Assign the input register
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MI->getOperand(OpNum).setReg(PhysReg); // Assign the input register
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return MI;
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}
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@ -599,7 +599,7 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
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DestPhysReg = getReg(MBB, MI, DestVirtReg);
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PhysRegsEverUsed[DestPhysReg] = true;
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markVirtRegModified(DestVirtReg);
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MI->SetMachineOperandReg(i, DestPhysReg); // Assign the output register
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MI->getOperand(i).setReg(DestPhysReg); // Assign the output register
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}
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}
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@ -211,7 +211,7 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
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Virt2PhysRegMap[virtualReg] = physReg;
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}
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}
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MI->SetMachineOperandReg(i, physReg);
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MI->getOperand(i).setReg(physReg);
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DEBUG(std::cerr << "virt: " << virtualReg <<
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", phys: " << op.getReg() << "\n");
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}
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@ -200,7 +200,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
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for (unsigned i = 1, e = mi->getNumOperands(); i != e; ++i) {
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if (mi->getOperand(i).isRegister() &&
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mi->getOperand(i).getReg() == regB)
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mi->SetMachineOperandReg(i, regA);
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mi->getOperand(i).setReg(regA);
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}
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}
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@ -182,7 +182,7 @@ bool SimpleSpiller::runOnMachineFunction(MachineFunction &MF, VirtRegMap &VRM) {
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}
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}
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PhysRegsUsed[PhysReg] = true;
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MI.SetMachineOperandReg(i, PhysReg);
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MI.getOperand(i).setReg(PhysReg);
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} else {
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PhysRegsUsed[MO.getReg()] = true;
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}
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@ -458,7 +458,7 @@ namespace {
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// Any stores to this stack slot are not dead anymore.
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MaybeDeadStores.erase(NewOp.StackSlot);
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MI->SetMachineOperandReg(NewOp.Operand, NewPhysReg);
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MI->getOperand(NewOp.Operand).setReg(NewPhysReg);
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Spills.addAvailable(NewOp.StackSlot, NewPhysReg);
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++NumLoads;
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@ -536,7 +536,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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// This virtual register was assigned a physreg!
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unsigned Phys = VRM.getPhys(VirtReg);
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PhysRegsUsed[Phys] = true;
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MI.SetMachineOperandReg(i, Phys);
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MI.getOperand(i).setReg(Phys);
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continue;
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}
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@ -567,7 +567,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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<< MRI->getName(PhysReg) << " for vreg"
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<< VirtReg <<" instead of reloading into physreg "
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<< MRI->getName(VRM.getPhys(VirtReg)) << "\n");
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MI.SetMachineOperandReg(i, PhysReg);
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MI.getOperand(i).setReg(PhysReg);
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// The only technical detail we have is that we don't know that
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// PhysReg won't be clobbered by a reloaded stack slot that occurs
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@ -618,7 +618,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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<< MRI->getName(PhysReg) << " for vreg"
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<< VirtReg
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<< " instead of reloading into same physreg.\n");
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MI.SetMachineOperandReg(i, PhysReg);
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MI.getOperand(i).setReg(PhysReg);
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++NumReused;
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continue;
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}
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@ -633,7 +633,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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Spills.ClobberPhysReg(DesignatedReg);
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Spills.addAvailable(StackSlot, DesignatedReg);
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MI.SetMachineOperandReg(i, DesignatedReg);
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MI.getOperand(i).setReg(DesignatedReg);
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DEBUG(std::cerr << '\t' << *prior(MII));
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++NumReused;
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continue;
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@ -662,7 +662,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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MaybeDeadStores.erase(StackSlot);
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Spills.addAvailable(StackSlot, PhysReg);
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++NumLoads;
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MI.SetMachineOperandReg(i, PhysReg);
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MI.getOperand(i).setReg(PhysReg);
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DEBUG(std::cerr << '\t' << *prior(MII));
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}
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@ -817,7 +817,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
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PhysRegsUsed[PhysReg] = true;
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MRI->storeRegToStackSlot(MBB, next(MII), PhysReg, StackSlot, RC);
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DEBUG(std::cerr << "Store:\t" << *next(MII));
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MI.SetMachineOperandReg(i, PhysReg);
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MI.getOperand(i).setReg(PhysReg);
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// Check to see if this is a noop copy. If so, eliminate the
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// instruction before considering the dest reg to be changed.
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@ -216,7 +216,7 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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// Add the base register of R30 (SP) or R15 (FP).
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MI.SetMachineOperandReg(i + 1, FP ? Alpha::R15 : Alpha::R30);
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MI.getOperand(i + 1).ChangeToRegister(FP ? Alpha::R15 : Alpha::R30);
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// Now add the frame object offset to the offset from the virtual frame index.
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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@ -233,15 +233,14 @@ AlphaRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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//so in this case, we need to use a temporary register, and move the original
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//inst off the SP/FP
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//fix up the old:
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MI.SetMachineOperandReg(i + 1, Alpha::R28);
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MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate,
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getLower16(Offset));
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MI.getOperand(i + 1).ChangeToRegister(Alpha::R28);
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MI.getOperand(i).ChangeToImmediate(getLower16(Offset));
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//insert the new
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MachineInstr* nMI=BuildMI(Alpha::LDAH, 2, Alpha::R28)
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.addImm(getUpper16(Offset)).addReg(FP ? Alpha::R15 : Alpha::R30);
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MBB.insert(II, nMI);
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} else {
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MI.SetMachineOperandConst(i, MachineOperand::MO_Immediate, Offset);
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MI.getOperand(i).ChangeToImmediate(Offset);
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}
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}
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@ -155,7 +155,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
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// choose a base register: ( hasFP? framepointer : stack pointer )
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unsigned BaseRegister = FP ? IA64::r5 : IA64::r12;
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// Add the base register
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MI.SetMachineOperandReg(i, BaseRegister);
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MI.getOperand(i).ChangeToRegister(BaseRegister);
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// Now add the frame object offset to the offset from r1.
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex);
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@ -168,7 +168,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
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// XXX: we use 'r22' as another hack+slash temporary register here :(
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if ( Offset <= 8191 && Offset >= -8192) { // smallish offset
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//fix up the old:
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MI.SetMachineOperandReg(i, IA64::r22);
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MI.getOperand(i).ChangeToRegister(IA64::r22);
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MI.getOperand(i).setUse(); // mark r22 as being used
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// (the bundler wants to know this)
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//insert the new
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@ -177,7 +177,7 @@ void IA64RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const
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MBB.insert(II, nMI);
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} else { // it's big
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//fix up the old:
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MI.SetMachineOperandReg(i, IA64::r22);
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MI.getOperand(i).ChangeToRegister(IA64::r22);
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MI.getOperand(i).setUse(); // mark r22 as being used
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// (the bundler wants to know this)
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MachineInstr* nMI;
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@ -136,8 +136,8 @@ MachineInstr *PPCInstrInfo::commuteInstruction(MachineInstr *MI) const {
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// Swap op1/op2
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unsigned Reg1 = MI->getOperand(1).getReg();
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unsigned Reg2 = MI->getOperand(2).getReg();
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MI->SetMachineOperandReg(2, Reg1);
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MI->SetMachineOperandReg(1, Reg2);
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MI->getOperand(2).setReg(Reg1);
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MI->getOperand(1).setReg(Reg2);
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// Swap the mask around.
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unsigned MB = MI->getOperand(4).getImmedValue();
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@ -294,7 +294,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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int FrameIndex = MI.getOperand(i).getFrameIndex();
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// Replace the FrameIndex with base register with GPR1 (SP) or GPR31 (FP).
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MI.SetMachineOperandReg(i, hasFP(MF) ? PPC::R31 : PPC::R1);
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MI.getOperand(i).ChangeToRegister(hasFP(MF) ? PPC::R31 : PPC::R1);
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// Take into account whether it's an add or mem instruction
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unsigned OffIdx = (i == 2) ? 1 : 2;
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@ -321,8 +321,8 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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"No indexed form of load or store available!");
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unsigned NewOpcode = ImmToIdxMap.find(MI.getOpcode())->second;
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MI.setOpcode(NewOpcode);
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MI.SetMachineOperandReg(1, MI.getOperand(i).getReg());
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MI.SetMachineOperandReg(2, PPC::R0);
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MI.getOperand(1).ChangeToRegister(MI.getOperand(i).getReg());
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MI.getOperand(2).ChangeToRegister(PPC::R0);
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} else {
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switch (MI.getOpcode()) {
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case PPC::LWA:
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@ -333,7 +333,7 @@ PPCRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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Offset >>= 2; // The actual encoded value has the low two bits zero.
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break;
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}
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MI.SetMachineOperandConst(OffIdx, MachineOperand::MO_Immediate, Offset);
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MI.getOperand(OffIdx).ChangeToImmediate(Offset);
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}
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}
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@ -104,8 +104,8 @@ bool FPMover::runOnMachineBasicBlock(MachineBasicBlock &MBB) {
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else
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assert(0 && "Unknown opcode!");
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MI->SetMachineOperandReg(0, EvenDestReg);
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MI->SetMachineOperandReg(1, EvenSrcReg);
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MI->getOperand(0).setReg(EvenDestReg);
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MI->getOperand(1).setReg(EvenSrcReg);
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DEBUG(std::cerr << "FPMover: the modified instr is: " << *MI);
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// Insert copy for the other half of the double.
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if (DestDReg != SrcDReg) {
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@ -135,8 +135,8 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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if (Offset >= -4096 && Offset <= 4095) {
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// If the offset is small enough to fit in the immediate field, directly
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// encode it.
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MI.SetMachineOperandReg(i, SP::I6);
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MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate, Offset);
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MI.getOperand(i).ChangeToRegister(SP::I6);
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MI.getOperand(i+1).ChangeToImmediate(Offset);
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} else {
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// Otherwise, emit a G1 = SETHI %hi(offset). FIXME: it would be better to
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// scavenge a register here instead of reserving G1 all of the time.
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@ -146,9 +146,8 @@ SparcRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const {
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BuildMI(*MI.getParent(), II, SP::ADDrr, 2,
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SP::G1).addReg(SP::G1).addReg(SP::I6);
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// Insert: G1+%lo(offset) into the user.
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MI.SetMachineOperandReg(i, SP::G1);
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MI.SetMachineOperandConst(i+1, MachineOperand::MO_Immediate,
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Offset & ((1 << 10)-1));
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MI.getOperand(i).ChangeToRegister(SP::G1);
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MI.getOperand(i+1).ChangeToImmediate(Offset & ((1 << 10)-1));
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}
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}
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@ -46,7 +46,7 @@ MachineInstr *TargetInstrInfo::commuteInstruction(MachineInstr *MI) const {
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"This only knows how to commute register operands so far");
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unsigned Reg1 = MI->getOperand(1).getReg();
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unsigned Reg2 = MI->getOperand(1).getReg();
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MI->SetMachineOperandReg(2, Reg1);
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MI->SetMachineOperandReg(1, Reg2);
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MI->getOperand(2).setReg(Reg1);
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MI->getOperand(1).setReg(Reg2);
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return MI;
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}
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@ -665,7 +665,7 @@ void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
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// This must be part of a four operand memory reference. Replace the
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// FrameIndex with base register with EBP. Add add an offset to the offset.
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MI.SetMachineOperandReg(i, hasFP(MF) ? X86::EBP : X86::ESP);
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MI.getOperand(i).ChangeToRegister(hasFP(MF) ? X86::EBP : X86::ESP);
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// Now add the frame object offset to the offset from EBP.
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int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
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@ -676,7 +676,7 @@ void X86RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II) const{
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else
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Offset += 4; // Skip the saved EBP
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MI.SetMachineOperandConst(i+3, MachineOperand::MO_Immediate, Offset);
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MI.getOperand(i+3).ChangeToImmediate(Offset);
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}
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void
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