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Fix i64 return, fix CopyFromReg

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@21076 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Nate Begeman
2005-04-04 06:52:38 +00:00
parent 6e02e6842a
commit e584668f04
1 changed files with 14 additions and 3 deletions
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15
lib/Target/PowerPC/PPCISelPattern.cpp
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@@ -172,8 +172,13 @@ PPC32TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) {
// We need to load the argument to a virtual register if we determined above // We need to load the argument to a virtual register if we determined above
// that we ran out of physical registers of the appropriate type // that we ran out of physical registers of the appropriate type
if (needsLoad) { if (needsLoad) {
unsigned SubregOffset = 0;
if (ObjectVT == MVT::i8) SubregOffset = 3;
if (ObjectVT == MVT::i16) SubregOffset = 2;
int FI = MFI->CreateFixedObject(ObjSize, ArgOffset); int FI = MFI->CreateFixedObject(ObjSize, ArgOffset);
SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32); SDOperand FIN = DAG.getFrameIndex(FI, MVT::i32);
FIN = DAG.getNode(ISD::ADD, MVT::i32, FIN,
DAG.getConstant(SubregOffset, MVT::i32));
argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN); argt = newroot = DAG.getLoad(ObjectVT, DAG.getEntryNode(), FIN);
} }
@@ -933,6 +938,9 @@ unsigned ISel::SelectExpr(SDOperand N) {
break; break;
} }
if (ISD::CopyFromReg == opcode)
DestType = N.getValue(0).getValueType();
if (DestType == MVT::f64 || DestType == MVT::f32) if (DestType == MVT::f64 || DestType == MVT::f32)
if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode && ISD::UNDEF != opcode) if (ISD::LOAD != opcode && ISD::EXTLOAD != opcode && ISD::UNDEF != opcode)
return SelectExprFP(N, Result); return SelectExprFP(N, Result);
@@ -1109,9 +1117,12 @@ unsigned ISel::SelectExpr(SDOperand N) {
case MVT::i8: case MVT::i8:
case MVT::i16: case MVT::i16:
case MVT::i32: case MVT::i32:
if (Node->getValueType(1) == MVT::i32) {
BuildMI(BB, PPC::OR, 2, Result+1).addReg(PPC::R3).addReg(PPC::R3);
BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R4).addReg(PPC::R4);
} else {
BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R3).addReg(PPC::R3); BuildMI(BB, PPC::OR, 2, Result).addReg(PPC::R3).addReg(PPC::R3);
if (Node->getValueType(1) == MVT::i32) }
BuildMI(BB, PPC::OR, 2, Result+1).addReg(PPC::R4).addReg(PPC::R4);
break; break;
case MVT::f32: case MVT::f32:
case MVT::f64: case MVT::f64: