Emit saveri with the correct operand order, patch by Richard Pennington!

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@54313 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2008-08-03 18:16:14 +00:00
parent 64cf160fef
commit e594fd473e

View File

@ -137,7 +137,7 @@ void SparcRegisterInfo::emitPrologue(MachineFunction &MF) const {
if (NumBytes >= -4096) {
BuildMI(MBB, MBB.begin(), TII.get(SP::SAVEri),
SP::O6).addImm(NumBytes).addReg(SP::O6);
SP::O6).addReg(SP::O6).addImm(NumBytes);
} else {
MachineBasicBlock::iterator InsertPt = MBB.begin();
// Emit this the hard way. This clobbers G1 which we always know is