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* Elimiante a bunch of functions from InstrSelectionSupport.h, replacing users
of them with BUildMI calls instead. * Fix def information in instructions generated by prologepilog inserter git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@5287 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -9,6 +9,7 @@
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/MachineFunctionInfo.h"
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#include "llvm/CodeGen/MachineCodeForInstruction.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/Function.h"
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#include "llvm/Constants.h"
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#include "llvm/DerivedTypes.h"
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@ -63,7 +64,7 @@ CreateSETUWConst(const TargetMachine& target, uint32_t C,
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{
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if (miSETHI)
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{ // unsigned value with high-order bits set using SETHI
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miOR = Create3OperandInstr_UImmed(OR, dest, C, dest);
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miOR = BuildMI(OR, 3).addReg(dest).addZImm(C).addReg(dest, MOTy::Def);
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miOR->setOperandLo32(1);
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}
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else
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@ -97,17 +98,13 @@ static inline void
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CreateSETSWConst(const TargetMachine& target, int32_t C,
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Instruction* dest, vector<MachineInstr*>& mvec)
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{
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MachineInstr* MI;
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// Set the low 32 bits of dest
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CreateSETUWConst(target, (uint32_t) C, dest, mvec, /*isSigned*/true);
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// Sign-extend to the high 32 bits if needed
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if (C < 0 && (-C) > (int32_t) MAXSIMM)
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{
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MI = Create3OperandInstr_UImmed(SRA, dest, 0, dest);
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mvec.push_back(MI);
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}
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mvec.push_back(BuildMI(SRA, 3).addReg(dest).addZImm(0).addReg(dest,
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MOTy::Def));
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}
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@ -134,15 +131,15 @@ CreateSETXConst(const TargetMachine& target, uint64_t C,
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CreateSETUWConst(target, (C >> 32), tmpReg, mvec);
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// Shift tmpReg left by 32 bits
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MI = Create3OperandInstr_UImmed(SLLX, tmpReg, 32, tmpReg);
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mvec.push_back(MI);
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mvec.push_back(BuildMI(SLLX, 3).addReg(tmpReg).addZImm(32).addReg(tmpReg,
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MOTy::Def));
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// Code to set the low 32 bits of the value in register `dest'
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CreateSETUWConst(target, C, dest, mvec);
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// dest = OR(tmpReg, dest)
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MI = Create3OperandInstr(OR, dest, tmpReg, dest);
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mvec.push_back(MI);
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mvec.push_back(BuildMI(OR, 3).addReg(dest).addReg(tmpReg).addReg(dest,
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MOTy::Def));
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}
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@ -164,7 +161,7 @@ CreateSETUWLabel(const TargetMachine& target, Value* val,
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mvec.push_back(MI);
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// Set the low 10 bits in dest
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MI = Create3OperandInstr(OR, dest, val, dest);
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MI = BuildMI(OR, 3).addReg(dest).addReg(val).addReg(dest, MOTy::Def);
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MI->setOperandLo32(1);
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mvec.push_back(MI);
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}
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@ -190,21 +187,20 @@ CreateSETXLabel(const TargetMachine& target,
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MI->setOperandHi64(0);
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mvec.push_back(MI);
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MI = Create3OperandInstr_Addr(OR, tmpReg, val, tmpReg);
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MI = BuildMI(OR, 3).addReg(tmpReg).addPCDisp(val).addReg(tmpReg, MOTy::Def);
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MI->setOperandLo64(1);
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mvec.push_back(MI);
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MI = Create3OperandInstr_UImmed(SLLX, tmpReg, 32, tmpReg);
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mvec.push_back(MI);
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mvec.push_back(BuildMI(SLLX, 3).addReg(tmpReg).addZImm(32).addReg(tmpReg,
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MOTy::Def));
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MI = Create2OperandInstr_Addr(SETHI, val, dest);
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MI->setOperandHi32(0);
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mvec.push_back(MI);
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MI = Create3OperandInstr(OR, dest, tmpReg, dest);
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MI = BuildMI(OR, 3).addReg(dest).addReg(tmpReg).addReg(dest, MOTy::Def);
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mvec.push_back(MI);
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MI = Create3OperandInstr_Addr(OR, dest, val, dest);
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MI = BuildMI(OR, 3).addReg(dest).addPCDisp(val).addReg(dest, MOTy::Def);
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MI->setOperandLo32(1);
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mvec.push_back(MI);
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}
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@ -456,10 +452,9 @@ UltraSparcInstrInfo::CreateCodeToLoadConst(const TargetMachine& target,
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// Generate the load instruction
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int64_t zeroOffset = 0; // to avoid ambiguity with (Value*) 0
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MachineInstr* MI =
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Create3OperandInstr_SImmed(ChooseLoadInstruction(val->getType()),
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addrReg, zeroOffset, dest);
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mvec.push_back(MI);
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unsigned Opcode = ChooseLoadInstruction(val->getType());
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mvec.push_back(BuildMI(Opcode, 3).addReg(addrReg).
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addSImm(zeroOffset).addReg(dest, MOTy::Def));
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// Make sure constant is emitted to constant pool in assembly code.
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MachineFunction::get(F).getInfo()->addToConstantPool(cast<Constant>(val));
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@ -630,12 +625,11 @@ UltraSparcInstrInfo::CreateCopyInstructionsByType(const TargetMachine& target,
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// Make `src' the second operand, in case it is a constant
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// Use (unsigned long) 0 for a NULL pointer value.
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//
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const Type* zeroValueType =
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isa<PointerType>(resultType) ? Type::ULongTy : resultType;
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MachineInstr* minstr =
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Create3OperandInstr(opCode, Constant::getNullValue(zeroValueType),
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src, dest);
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mvec.push_back(minstr);
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const Type* Ty =isa<PointerType>(resultType) ? Type::ULongTy : resultType;
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MachineInstr* MI =
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BuildMI(opCode, 3).addReg(Constant::getNullValue(Ty))
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.addReg(src).addReg(dest, MOTy::Def);
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mvec.push_back(MI);
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}
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}
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@ -661,14 +655,13 @@ CreateBitExtensionInstructions(bool signExtend,
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TmpInstruction *tmpI = new TmpInstruction(destVal->getType(),
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srcVal, destVal, "make32");
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mcfi.addTemp(tmpI);
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M = Create3OperandInstr_UImmed(SLLX, srcVal, 32-numLowBits, tmpI);
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mvec.push_back(M);
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mvec.push_back(BuildMI(SLLX, 3).addReg(srcVal).addZImm(32-numLowBits)
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.addReg(tmpI, MOTy::Def));
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srcVal = tmpI;
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}
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M = Create3OperandInstr_UImmed(signExtend? SRA : SRL,
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srcVal, 32-numLowBits, destVal);
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mvec.push_back(M);
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mvec.push_back(BuildMI(signExtend? SRA : SRL, 3).addReg(srcVal)
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.addZImm(32-numLowBits).addReg(destVal, MOTy::Def));
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}
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@ -8,7 +8,7 @@
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#include "SparcInstrSelectionSupport.h"
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#include "SparcRegClassInfo.h"
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#include "llvm/CodeGen/InstrSelectionSupport.h"
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#include "llvm/CodeGen/MachineInstr.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineInstrAnnot.h"
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#include "llvm/CodeGen/InstrForest.h"
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#include "llvm/CodeGen/InstrSelection.h"
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@ -546,8 +546,10 @@ CreateShiftInstructions(const TargetMachine& target,
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}
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MachineInstr* M = (optArgVal2 != NULL)
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? Create3OperandInstr(shiftOpCode, argVal1, optArgVal2, shiftDest)
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: Create3OperandInstr_UImmed(shiftOpCode, argVal1, optShiftNum, shiftDest);
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? BuildMI(shiftOpCode, 3).addReg(argVal1).addReg(optArgVal2)
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.addReg(shiftDest, MOTy::Def)
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: BuildMI(shiftOpCode, 3).addReg(argVal1).addZImm(optShiftNum)
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.addReg(shiftDest, MOTy::Def);
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mvec.push_back(M);
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if (shiftDest != destVal)
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@ -601,14 +603,10 @@ CreateMulConstInstruction(const TargetMachine &target, Function* F,
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if (C == 0 || C == 1)
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{
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cost = target.getInstrInfo().minLatency(ADD);
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unsigned ZeroReg = target.getRegInfo().getZeroRegNum();
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MachineInstr* M = (C == 0)
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? Create3OperandInstr_Reg(ADD,
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target.getRegInfo().getZeroRegNum(),
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target.getRegInfo().getZeroRegNum(),
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destVal)
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: Create3OperandInstr_Reg(ADD, lval,
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target.getRegInfo().getZeroRegNum(),
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destVal);
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? Create3OperandInstr_Reg(ADD, ZeroReg, ZeroReg, destVal)
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: Create3OperandInstr_Reg(ADD, lval, ZeroReg, destVal);
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mvec.push_back(M);
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}
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else if (isPowerOf2(C, pow))
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@ -1728,10 +1726,11 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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M->SetMachineOperandVal(2, MachineOperand::MO_VirtualRegister,quot);
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mvec.push_back(M);
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M = Create3OperandInstr(ChooseMulInstructionByType(
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subtreeRoot->getInstruction()->getType()),
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quot, subtreeRoot->rightChild()->getValue(),
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prod);
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unsigned MulOpcode =
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ChooseMulInstructionByType(subtreeRoot->getInstruction()->getType());
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Value *MulRHS = subtreeRoot->rightChild()->getValue();
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M = BuildMI(MulOpcode, 3).addReg(quot).addReg(MulRHS).addReg(prod,
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MOTy::Def);
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mvec.push_back(M);
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M = new MachineInstr(ChooseSubInstructionByType(
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@ -1759,9 +1758,10 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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Value* notArg = BinaryOperator::getNotArgument(
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cast<BinaryOperator>(notNode->getInstruction()));
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notNode->markFoldedIntoParent();
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mvec.push_back(Create3OperandInstr(ANDN,
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subtreeRoot->leftChild()->getValue(),
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notArg, subtreeRoot->getValue()));
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Value *LHS = subtreeRoot->leftChild()->getValue();
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Value *Dest = subtreeRoot->getValue();
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mvec.push_back(BuildMI(ANDN, 3).addReg(LHS).addReg(notArg)
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.addReg(Dest, MOTy::Def));
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break;
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}
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@ -1781,9 +1781,10 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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Value* notArg = BinaryOperator::getNotArgument(
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cast<BinaryOperator>(notNode->getInstruction()));
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notNode->markFoldedIntoParent();
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mvec.push_back(Create3OperandInstr(ORN,
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subtreeRoot->leftChild()->getValue(),
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notArg, subtreeRoot->getValue()));
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Value *LHS = subtreeRoot->leftChild()->getValue();
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Value *Dest = subtreeRoot->getValue();
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mvec.push_back(BuildMI(ORN, 3).addReg(LHS).addReg(notArg)
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.addReg(Dest, MOTy::Def));
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break;
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}
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@ -1803,9 +1804,10 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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Value* notArg = BinaryOperator::getNotArgument(
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cast<BinaryOperator>(notNode->getInstruction()));
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notNode->markFoldedIntoParent();
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mvec.push_back(Create3OperandInstr(XNOR,
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subtreeRoot->leftChild()->getValue(),
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notArg, subtreeRoot->getValue()));
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Value *LHS = subtreeRoot->leftChild()->getValue();
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Value *Dest = subtreeRoot->getValue();
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mvec.push_back(BuildMI(XNOR, 3).addReg(LHS).addReg(notArg)
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.addReg(Dest, MOTy::Def));
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break;
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}
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@ -2010,8 +2012,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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if (isa<Function>(callee)) // direct function call
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M = Create1OperandInstr_Addr(CALL, callee);
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else // indirect function call
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M = Create3OperandInstr_SImmed(JMPLCALL, callee,
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(int64_t) 0, retAddrReg);
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M = BuildMI(JMPLCALL,
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3).addReg(callee).addSImm((int64_t)0).addReg(retAddrReg);
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mvec.push_back(M);
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const FunctionType* funcType =
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@ -2172,7 +2174,8 @@ GetInstructionsByRule(InstructionNode* subtreeRoot,
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for (unsigned i=0, N=mvec.size(); i < N; ++i)
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mvec[i]->substituteValue(dest, tmpI);
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M = Create3OperandInstr_UImmed(SRL, tmpI, 8*(4-destSize), dest);
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M = BuildMI(SRL, 3).addReg(tmpI).addZImm(8*(4-destSize))
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.addReg(dest, MOTy::Def);
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mvec.push_back(M);
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}
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else if (destSize < target.getTargetData().getIntegerRegize())
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@ -63,7 +63,8 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
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int32_t C = - (int) staticStackSize;
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int SP = TM.getRegInfo().getStackPointer();
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if (TM.getInstrInfo().constantFitsInImmedField(SAVE, staticStackSize)) {
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mvec.push_back(BuildMI(SAVE, 3).addMReg(SP).addSImm(C).addMReg(SP));
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mvec.push_back(BuildMI(SAVE, 3).addMReg(SP).addSImm(C).addMReg(SP,
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MOTy::Def));
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} else {
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// We have to put the stack size value into a register before SAVE.
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// Use register %g1 since it is volatile across calls. Note that the
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@ -74,19 +75,19 @@ void InsertPrologEpilogCode::InsertPrologCode(MachineFunction &MF)
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TM.getRegInfo().getRegClassIDOfType(Type::IntTy),
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SparcIntRegClass::g1);
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MachineInstr* M = BuildMI(SETHI, 2).addSImm(C).addMReg(uregNum);
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MachineInstr* M = BuildMI(SETHI, 2).addSImm(C).addMReg(uregNum, MOTy::Def);
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M->setOperandHi32(0);
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mvec.push_back(M);
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M = BuildMI(OR, 3).addMReg(uregNum).addSImm(C).addMReg(uregNum);
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M = BuildMI(OR, 3).addMReg(uregNum).addSImm(C).addMReg(uregNum, MOTy::Def);
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M->setOperandLo32(1);
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mvec.push_back(M);
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M = BuildMI(SRA, 3).addMReg(uregNum).addZImm(0).addMReg(uregNum);
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M = BuildMI(SRA, 3).addMReg(uregNum).addZImm(0).addMReg(uregNum, MOTy::Def);
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mvec.push_back(M);
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// Now generate the SAVE using the value in register %g1
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M = BuildMI(SAVE, 3).addMReg(SP).addMReg(uregNum).addMReg(SP);
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M = BuildMI(SAVE, 3).addMReg(SP).addMReg(uregNum).addMReg(SP, MOTy::Def);
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mvec.push_back(M);
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}
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@ -106,7 +107,7 @@ void InsertPrologEpilogCode::InsertEpilogCode(MachineFunction &MF)
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{
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int ZR = TM.getRegInfo().getZeroRegNum();
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MachineInstr *Restore =
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BuildMI(RESTORE, 3).addMReg(ZR).addSImm(0).addMReg(ZR);
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BuildMI(RESTORE, 3).addMReg(ZR).addSImm(0).addMReg(ZR, MOTy::Def);
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MachineCodeForInstruction &termMvec =
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MachineCodeForInstruction::get(TermInst);
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