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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-18 12:29:21 +00:00
Added opcode conversion for conditional move of integers.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@6567 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -117,6 +117,51 @@ convertOpcodeFromRegToImm(unsigned Opcode) {
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case V9::SRLXr6: return V9::SRLXi6;
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case V9::SRAXr6: return V9::SRAXi6;
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/* Conditional move on int comparison with zero */
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case V9::MOVRZr: return V9::MOVRZi;
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case V9::MOVRLEZr: return V9::MOVRLEZi;
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case V9::MOVRLZr: return V9::MOVRLZi;
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case V9::MOVRNZr: return V9::MOVRNZi;
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case V9::MOVRGZr: return V9::MOVRGZi;
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case V9::MOVRGEZr: return V9::MOVRGEZi;
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/* Conditional move on int condition code */
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case V9::MOVAr: return V9::MOVAi;
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case V9::MOVNr: return V9::MOVNi;
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case V9::MOVNEr: return V9::MOVNEi;
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case V9::MOVEr: return V9::MOVEi;
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case V9::MOVGr: return V9::MOVGi;
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case V9::MOVLEr: return V9::MOVLEi;
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case V9::MOVGEr: return V9::MOVGEi;
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case V9::MOVLr: return V9::MOVLi;
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case V9::MOVGUr: return V9::MOVGUi;
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case V9::MOVLEUr: return V9::MOVLEUi;
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case V9::MOVCCr: return V9::MOVCCi;
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case V9::MOVCSr: return V9::MOVCSi;
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case V9::MOVPOSr: return V9::MOVPOSi;
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case V9::MOVNEGr: return V9::MOVNEGi;
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case V9::MOVVCr: return V9::MOVVCi;
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case V9::MOVVSr: return V9::MOVVSi;
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/* Conditional move of int reg on fp condition code */
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case V9::MOVFAr: return V9::MOVFAi;
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case V9::MOVFNr: return V9::MOVFNi;
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case V9::MOVFUr: return V9::MOVFUi;
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case V9::MOVFGr: return V9::MOVFGi;
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case V9::MOVFUGr: return V9::MOVFUGi;
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case V9::MOVFLr: return V9::MOVFLi;
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case V9::MOVFULr: return V9::MOVFULi;
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case V9::MOVFLGr: return V9::MOVFLGi;
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case V9::MOVFNEr: return V9::MOVFNEi;
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case V9::MOVFEr: return V9::MOVFEi;
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case V9::MOVFUEr: return V9::MOVFUEi;
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case V9::MOVFGEr: return V9::MOVFGEi;
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case V9::MOVFUGEr: return V9::MOVFUGEi;
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case V9::MOVFLEr: return V9::MOVFLEi;
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case V9::MOVFULEr: return V9::MOVFULEi;
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case V9::MOVFOr: return V9::MOVFOi;
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/* load */
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case V9::LDSBr: return V9::LDSBi;
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case V9::LDSHr: return V9::LDSHi;
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@ -152,6 +197,11 @@ convertOpcodeFromRegToImm(unsigned Opcode) {
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default:
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// It's already in correct format
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// Or, it's just not handled yet, but an assert() would break LLC
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#if 0
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std::cerr << "Unhandled opcode in convertOpcodeFromRegToImm(): " << Opcode
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<< "\n";
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#endif
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return Opcode;
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}
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}
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