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SparcV8 skeleton
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11828 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
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55
lib/Target/Sparc/Makefile
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55
lib/Target/Sparc/Makefile
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##===- lib/Target/SparcV8/Makefile -------------------------*- Makefile -*-===##
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#
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# The LLVM Compiler Infrastructure
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#
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# This file was developed by the LLVM research group and is distributed under
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# the University of Illinois Open Source License. See LICENSE.TXT for details.
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#
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##===----------------------------------------------------------------------===##
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LEVEL = ../../..
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LIBRARYNAME = sparcv8
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include $(LEVEL)/Makefile.common
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# Make sure that tblgen is run, first thing.
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$(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
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SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
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SparcV8GenInstrInfo.inc SparcV8GenInstrSelector.inc
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SparcV8GenRegisterNames.inc:: $(SourceDir)/SparcV8.td \
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$(SourceDir)/SparcV8Reg.td \
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$(SourceDir)/../Target.td $(TBLGEN)
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@echo "Building SparcV8.td register names with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
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SparcV8GenRegisterInfo.h.inc:: $(SourceDir)/SparcV8.td \
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$(SourceDir)/SparcV8Reg.td \
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$(SourceDir)/../Target.td $(TBLGEN)
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@echo "Building SparcV8.td register information header with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
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SparcV8GenRegisterInfo.inc:: $(SourceDir)/SparcV8.td \
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$(SourceDir)/SparcV8Reg.td \
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$(SourceDir)/../Target.td $(TBLGEN)
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@echo "Building SparcV8.td register information implementation with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
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SparcV8GenInstrNames.inc:: $(SourceDir)/SparcV8.td \
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$(SourceDir)/SparcV8Instrs.td \
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$(SourceDir)/../Target.td $(TBLGEN)
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@echo "Building SparcV8.td instruction names with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
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SparcV8GenInstrInfo.inc:: $(SourceDir)/SparcV8.td \
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$(SourceDir)/SparcV8Instrs.td \
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$(SourceDir)/../Target.td $(TBLGEN)
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@echo "Building SparcV8.td instruction information with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
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SparcV8GenInstrSelector.inc:: $(SourceDir)/SparcV8.td \
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$(SourceDir)/SparcV8Instrs.td \
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$(SourceDir)/../Target.td $(TBLGEN)
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@echo "Building SparcV8.td instruction selector with tblgen"
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$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
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clean::
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$(VERB) rm -f *.inc
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9
lib/Target/Sparc/README.txt
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9
lib/Target/Sparc/README.txt
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SparcV8 backend skeleton
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------------------------
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This directory will house a 32-bit SPARC V8 backend employing a expander-based
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instruction selector. Watch this space for more news coming soon!
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$Date$
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42
lib/Target/Sparc/Sparc.h
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42
lib/Target/Sparc/Sparc.h
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//===-- SparcV8.h - Top-level interface for SparcV8 representation -*- C++ -*-//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the entry points for global functions defined in the LLVM
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// SparcV8 back-end.
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//
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//===----------------------------------------------------------------------===//
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#ifndef TARGET_SPARCV8_H
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#define TARGET_SPARCV8_H
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#include <iosfwd>
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namespace llvm {
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class FunctionPass;
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class TargetMachine;
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// Here is where you would define factory methods for sparcv8-specific
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// passes. For example:
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// FunctionPass *createSparcV8SimpleInstructionSelector (TargetMachine &TM);
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// FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
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// TargetMachine &TM);
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} // end namespace llvm;
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// Defines symbolic names for SparcV8 registers. This defines a mapping from
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// register name to register number.
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//
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#include "SparcV8GenRegisterNames.inc"
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// Defines symbolic names for the SparcV8 instructions.
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//
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#include "SparcV8GenInstrNames.inc"
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#endif
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41
lib/Target/Sparc/Sparc.td
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41
lib/Target/Sparc/Sparc.td
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//===- SparcV8.td - Describe the SparcV8 Target Machine ---------*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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//
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//===----------------------------------------------------------------------===//
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// Get the target-independent interfaces which we are implementing...
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//
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include "../Target.td"
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//===----------------------------------------------------------------------===//
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// Register File Description
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//===----------------------------------------------------------------------===//
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include "SparcV8Reg.td"
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include "SparcV8Instrs.td"
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def SparcV8InstrInfo : InstrInfo {
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let PHIInst = PHI;
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}
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def SparcV8 : Target {
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// Pointers are 32-bits in size.
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let PointerType = i32;
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// According to the Mach-O Runtime ABI, these regs are nonvolatile across
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// calls:
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let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
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R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
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F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
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F30, F31, CR2, CR3, CR4];
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// Pull in Instruction Info:
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let InstructionSet = SparcV8InstrInfo;
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}
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42
lib/Target/Sparc/SparcInstrInfo.cpp
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lib/Target/Sparc/SparcInstrInfo.cpp
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//===- SparcV8InstrInfo.cpp - SparcV8 Instruction Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SparcV8 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcV8InstrInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "SparcV8GenInstrInfo.inc"
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namespace llvm {
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SparcV8InstrInfo::SparcV8InstrInfo()
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: TargetInstrInfo(SparcV8Insts,
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sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0]), 0) {
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}
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// createNOPinstr - returns the target's implementation of NOP, which is
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// usually a pseudo-instruction, implemented by a degenerate version of
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// another instruction.
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//
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MachineInstr* SparcV8InstrInfo::createNOPinstr() const {
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return 0;
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}
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/// isNOPinstr - not having a special NOP opcode, we need to know if a given
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/// instruction is interpreted as an `official' NOP instr, i.e., there may be
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/// more than one way to `do nothing' but only one canonical way to slack off.
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//
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bool SparcV8InstrInfo::isNOPinstr(const MachineInstr &MI) const {
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return false;
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}
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} // end namespace llvm
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48
lib/Target/Sparc/SparcInstrInfo.h
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48
lib/Target/Sparc/SparcInstrInfo.h
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//===- SparcV8InstrInfo.h - SparcV8 Instruction Information -----*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SparcV8 implementation of the TargetInstrInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPARCV8INSTRUCTIONINFO_H
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#define SPARCV8INSTRUCTIONINFO_H
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#include "llvm/Target/TargetInstrInfo.h"
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#include "SparcV8RegisterInfo.h"
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namespace llvm {
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class SparcV8InstrInfo : public TargetInstrInfo {
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const SparcV8RegisterInfo RI;
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public:
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SparcV8InstrInfo();
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/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
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/// such, whenever a client has an instance of instruction info, it should
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/// always be able to get register info as well (through this method).
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///
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virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
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/// createNOPinstr - returns the target's implementation of NOP, which is
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/// usually a pseudo-instruction, implemented by a degenerate version of
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/// another instruction.
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///
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MachineInstr* createNOPinstr() const;
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/// isNOPinstr - not having a special NOP opcode, we need to know if a given
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/// instruction is interpreted as an `official' NOP instr, i.e., there may be
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/// more than one way to `do nothing' but only one canonical way to slack off.
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///
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bool isNOPinstr(const MachineInstr &MI) const;
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};
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}
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#endif
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99
lib/Target/Sparc/SparcRegisterInfo.cpp
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99
lib/Target/Sparc/SparcRegisterInfo.cpp
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//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file was developed by the LLVM research group and is distributed under
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SparcV8 implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#include "SparcV8.h"
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#include "SparcV8RegisterInfo.h"
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#include "llvm/Type.h"
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using namespace llvm;
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SparcV8RegisterInfo::SparcV8RegisterInfo()
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: SparcV8GenRegisterInfo(SparcV8::ADJCALLSTACKDOWN,
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SparcV8::ADJCALLSTACKUP) {}
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int SparcV8RegisterInfo::storeRegToStackSlot(
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, int FrameIdx,
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const TargetRegisterClass *RC) const
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{
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abort();
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return -1;
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}
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int SparcV8RegisterInfo::loadRegFromStackSlot(
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MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIdx,
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const TargetRegisterClass *RC) const
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{
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abort();
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return -1;
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}
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int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned DestReg, unsigned SrcReg,
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const TargetRegisterClass *RC) const {
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abort();
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return -1;
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}
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void SparcV8RegisterInfo::
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eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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abort();
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}
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void
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SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
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MachineBasicBlock::iterator II) const {
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abort();
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}
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void SparcV8RegisterInfo::processFunctionBeforeFrameFinalized(
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MachineFunction &MF) const {
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abort();
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}
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void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
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abort();
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}
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void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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abort();
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}
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#include "SparcV8GenRegisterInfo.inc"
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const TargetRegisterClass*
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SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
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switch (Ty->getPrimitiveID()) {
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case Type::LongTyID:
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case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
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default: assert(0 && "Invalid type to getClass!");
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case Type::BoolTyID:
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case Type::SByteTyID:
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case Type::UByteTyID:
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case Type::ShortTyID:
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case Type::UShortTyID:
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case Type::IntTyID:
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case Type::UIntTyID:
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case Type::PointerTyID: return &GPRCInstance;
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case Type::FloatTyID:
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case Type::DoubleTyID: return &FPRCInstance;
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}
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}
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58
lib/Target/Sparc/SparcRegisterInfo.h
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58
lib/Target/Sparc/SparcRegisterInfo.h
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//===- SparcV8RegisterInfo.h - SparcV8 Register Information Impl -*- C++ -*-==//
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//
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// The LLVM Compiler Infrastructure
|
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//
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// This file was developed by the LLVM research group and is distributed under
|
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// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
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//===----------------------------------------------------------------------===//
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//
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// This file contains the SparcV8 implementation of the MRegisterInfo class.
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//
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//===----------------------------------------------------------------------===//
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#ifndef SPARCV8REGISTERINFO_H
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#define SPARCV8REGISTERINFO_H
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#include "llvm/Target/MRegisterInfo.h"
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#include "SparcV8GenRegisterInfo.h.inc"
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namespace llvm {
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class Type;
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struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
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SparcV8RegisterInfo();
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const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
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/// Code Generation virtual methods...
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int storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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unsigned SrcReg, int FrameIndex,
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
int loadRegFromStackSlot(MachineBasicBlock &MBB,
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||||
MachineBasicBlock::iterator MBBI,
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unsigned DestReg, int FrameIndex,
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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||||
unsigned DestReg, unsigned SrcReg,
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||||
const TargetRegisterClass *RC) const;
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||||
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||||
void eliminateCallFramePseudoInstr(MachineFunction &MF,
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||||
MachineBasicBlock &MBB,
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||||
MachineBasicBlock::iterator I) const;
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||||
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||||
void eliminateFrameIndex(MachineFunction &MF,
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||||
MachineBasicBlock::iterator II) const;
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||||
|
||||
void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
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||||
void emitPrologue(MachineFunction &MF) const;
|
||||
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
|
||||
};
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||||
|
||||
} // end namespace llvm
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||||
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||||
#endif
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61
lib/Target/Sparc/SparcTargetMachine.cpp
Normal file
61
lib/Target/Sparc/SparcTargetMachine.cpp
Normal file
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//===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===//
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//
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||||
// The LLVM Compiler Infrastructure
|
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//
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||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
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||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
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||||
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#include "SparcV8TargetMachine.h"
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#include "SparcV8.h"
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#include "llvm/Module.h"
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#include "llvm/PassManager.h"
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#include "llvm/Target/TargetMachineImpls.h"
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#include "llvm/CodeGen/MachineFunction.h"
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#include "llvm/CodeGen/Passes.h"
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namespace llvm {
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// allocateSparcV8TargetMachine - Allocate and return a subclass of
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// TargetMachine that implements the SparcV8 backend.
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//
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||||
TargetMachine *allocateSparcV8TargetMachine(const Module &M,
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IntrinsicLowering *IL) {
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return new SparcV8TargetMachine(M, IL);
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||||
}
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||||
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||||
/// SparcV8TargetMachine ctor - Create an ILP32 architecture model
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||||
///
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||||
SparcV8TargetMachine::SparcV8TargetMachine(const Module &M,
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||||
IntrinsicLowering *IL)
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||||
: TargetMachine("SparcV8", IL, true, 4, 4, 4, 4, 4),
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||||
FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 4), JITInfo(*this) {
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||||
}
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||||
|
||||
/// addPassesToEmitAssembly - Add passes to the specified pass manager
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||||
/// to implement a static compiler for this target.
|
||||
///
|
||||
bool SparcV8TargetMachine::addPassesToEmitAssembly(PassManager &PM,
|
||||
std::ostream &Out) {
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||||
// <insert instruction selector passes here>
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||||
PM.add(createRegisterAllocator());
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||||
PM.add(createPrologEpilogCodeInserter());
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||||
// <insert assembly code output passes here>
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||||
PM.add(createMachineCodeDeleter());
|
||||
return true; // change to `return false' when this actually works.
|
||||
}
|
||||
|
||||
/// addPassesToJITCompile - Add passes to the specified pass manager to
|
||||
/// implement a fast dynamic compiler for this target.
|
||||
///
|
||||
void SparcV8JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
|
||||
// <insert instruction selector passes here>
|
||||
PM.add(createRegisterAllocator());
|
||||
PM.add(createPrologEpilogCodeInserter());
|
||||
}
|
||||
|
||||
} // end namespace llvm
|
61
lib/Target/Sparc/SparcTargetMachine.h
Normal file
61
lib/Target/Sparc/SparcTargetMachine.h
Normal file
@ -0,0 +1,61 @@
|
||||
//===-- SparcV8TargetMachine.h - Define TargetMachine for SparcV8 -*- C++ -*-=//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file declares the SparcV8 specific subclass of TargetMachine.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef SPARCV8TARGETMACHINE_H
|
||||
#define SPARCV8TARGETMACHINE_H
|
||||
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/Target/TargetFrameInfo.h"
|
||||
#include "llvm/PassManager.h"
|
||||
#include "SparcV8InstrInfo.h"
|
||||
#include "SparcV8JITInfo.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class IntrinsicLowering;
|
||||
|
||||
class SparcV8TargetMachine : public TargetMachine {
|
||||
SparcV8InstrInfo InstrInfo;
|
||||
TargetFrameInfo FrameInfo;
|
||||
SparcV8JITInfo JITInfo;
|
||||
public:
|
||||
SparcV8TargetMachine(const Module &M, IntrinsicLowering *IL);
|
||||
|
||||
virtual const SparcV8InstrInfo &getInstrInfo() const { return InstrInfo; }
|
||||
virtual const TargetFrameInfo &getFrameInfo() const { return FrameInfo; }
|
||||
virtual const MRegisterInfo *getRegisterInfo() const {
|
||||
return &InstrInfo.getRegisterInfo();
|
||||
}
|
||||
virtual TargetJITInfo *getJITInfo() {
|
||||
return &JITInfo;
|
||||
}
|
||||
|
||||
virtual const TargetSchedInfo &getSchedInfo() const { abort(); }
|
||||
virtual const TargetRegInfo &getRegInfo() const { abort(); }
|
||||
virtual const TargetCacheInfo &getCacheInfo() const { abort(); }
|
||||
|
||||
/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
|
||||
/// get machine code emitted. This uses a MachineCodeEmitter object to handle
|
||||
/// actually outputting the machine code and resolving things like the address
|
||||
/// of functions. This method should returns true if machine code emission is
|
||||
/// not supported.
|
||||
///
|
||||
virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
|
||||
MachineCodeEmitter &MCE);
|
||||
|
||||
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
#endif
|
43
lib/Target/Sparc/SparcV8CodeEmitter.cpp
Normal file
43
lib/Target/Sparc/SparcV8CodeEmitter.cpp
Normal file
@ -0,0 +1,43 @@
|
||||
//===-- SparcV8CodeEmitter.cpp - JIT Code Emitter for SparcV8 -----*- C++ -*-=//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "SparcV8TargetMachine.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
/// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
|
||||
/// machine code emitted. This uses a MachineCodeEmitter object to handle
|
||||
/// actually outputting the machine code and resolving things like the address
|
||||
/// of functions. This method should returns true if machine code emission is
|
||||
/// not supported.
|
||||
///
|
||||
bool SparcV8TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
|
||||
MachineCodeEmitter &MCE) {
|
||||
return true;
|
||||
// It should go something like this:
|
||||
// PM.add(new Emitter(MCE)); // Machine code emitter pass for SparcV8
|
||||
// Delete machine code for this function after emitting it:
|
||||
// PM.add(createMachineCodeDeleter());
|
||||
}
|
||||
|
||||
void *SparcV8JITInfo::getJITStubForFunction(Function *F,
|
||||
MachineCodeEmitter &MCE) {
|
||||
assert (0 && "SparcV8JITInfo::getJITStubForFunction not implemented");
|
||||
return 0;
|
||||
}
|
||||
|
||||
void SparcV8JITInfo::replaceMachineCodeForFunction (void *Old, void *New) {
|
||||
assert (0 && "SparcV8JITInfo::replaceMachineCodeForFunction not implemented");
|
||||
}
|
||||
|
||||
} // end llvm namespace
|
||||
|
46
lib/Target/Sparc/SparcV8Instrs.td
Normal file
46
lib/Target/Sparc/SparcV8Instrs.td
Normal file
@ -0,0 +1,46 @@
|
||||
//===- SparcV8InstrInfo.td - Describe the SparcV8 Instruction Set -*- C++ -*-=//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class Format<bits<4> val> {
|
||||
bits<4> Value = val;
|
||||
}
|
||||
|
||||
// All of the SparcV8 instruction formats, plus a pseudo-instruction format:
|
||||
def Pseudo : Format<0>;
|
||||
def IForm : Format<1>;
|
||||
def BForm : Format<2>;
|
||||
def SCForm : Format<3>;
|
||||
def DForm : Format<4>;
|
||||
def XForm : Format<5>;
|
||||
def XLForm : Format<6>;
|
||||
def XFXForm : Format<7>;
|
||||
def XFLForm : Format<8>;
|
||||
def XOForm : Format<9>;
|
||||
def AForm : Format<10>;
|
||||
def MForm : Format<11>;
|
||||
|
||||
class PPCInst<string nm, bits<6> opcd, Format f> : Instruction {
|
||||
let Namespace = "SparcV8";
|
||||
|
||||
let Name = nm;
|
||||
bits<6> Opcode = opcd;
|
||||
Format Form = f;
|
||||
bits<4> FormBits = Form.Value;
|
||||
}
|
||||
|
||||
// Pseudo-instructions:
|
||||
def PHI : PPCInst<"PHI", 0, Pseudo>; // PHI node...
|
||||
def NOP : PPCInst<"NOP", 0, Pseudo>; // No-op
|
||||
def ADJCALLSTACKDOWN : PPCInst<"ADJCALLSTACKDOWN", 0, Pseudo>;
|
||||
def ADJCALLSTACKUP : PPCInst<"ADJCALLSTACKUP", 0, Pseudo>;
|
||||
|
||||
|
49
lib/Target/Sparc/SparcV8JITInfo.h
Normal file
49
lib/Target/Sparc/SparcV8JITInfo.h
Normal file
@ -0,0 +1,49 @@
|
||||
//===- SparcV8JITInfo.h - SparcV8 impl. of the JIT interface ----*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file contains the SparcV8 implementation of the TargetJITInfo class.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef SPARCV8JITINFO_H
|
||||
#define SPARCV8JITINFO_H
|
||||
|
||||
#include "llvm/Target/TargetJITInfo.h"
|
||||
|
||||
namespace llvm {
|
||||
class TargetMachine;
|
||||
class IntrinsicLowering;
|
||||
|
||||
class SparcV8JITInfo : public TargetJITInfo {
|
||||
TargetMachine &TM;
|
||||
public:
|
||||
SparcV8JITInfo(TargetMachine &tm) : TM(tm) {}
|
||||
|
||||
/// addPassesToJITCompile - Add passes to the specified pass manager to
|
||||
/// implement a fast dynamic compiler for this target. Return true if this
|
||||
/// is not supported for this target.
|
||||
///
|
||||
virtual void addPassesToJITCompile(FunctionPassManager &PM);
|
||||
|
||||
/// replaceMachineCodeForFunction - Make it so that calling the function
|
||||
/// whose machine code is at OLD turns into a call to NEW, perhaps by
|
||||
/// overwriting OLD with a branch to NEW. This is used for self-modifying
|
||||
/// code.
|
||||
///
|
||||
virtual void replaceMachineCodeForFunction(void *Old, void *New);
|
||||
|
||||
/// getJITStubForFunction - Create or return a stub for the specified
|
||||
/// function. This stub acts just like the specified function, except that
|
||||
/// it allows the "address" of the function to be taken without having to
|
||||
/// generate code for it.
|
||||
virtual void *getJITStubForFunction(Function *F, MachineCodeEmitter &MCE);
|
||||
};
|
||||
}
|
||||
|
||||
#endif
|
82
lib/Target/Sparc/SparcV8Reg.td
Normal file
82
lib/Target/Sparc/SparcV8Reg.td
Normal file
@ -0,0 +1,82 @@
|
||||
//===- SparcV8Reg.td - Describe the SparcV8 Register File -------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class PPCReg : Register {
|
||||
let Namespace = "SparcV8";
|
||||
}
|
||||
|
||||
// We identify all our registers with a 5-bit ID, for consistency's sake.
|
||||
|
||||
// GPR - One of the 32 32-bit general-purpose registers
|
||||
class GPR<bits<5> num> : PPCReg {
|
||||
field bits<5> Num = num;
|
||||
}
|
||||
|
||||
// SPR - One of the 32-bit special-purpose registers
|
||||
class SPR<bits<5> num> : PPCReg {
|
||||
field bits<5> Num = num;
|
||||
}
|
||||
|
||||
// FPR - One of the 32 64-bit floating-point registers
|
||||
class FPR<bits<5> num> : PPCReg {
|
||||
field bits<5> Num = num;
|
||||
}
|
||||
|
||||
// CR - One of the 8 4-bit condition registers
|
||||
class CR<bits<5> num> : PPCReg {
|
||||
field bits<5> Num = num;
|
||||
}
|
||||
|
||||
// General-purpose registers
|
||||
def R0 : GPR< 0>; def R1 : GPR< 1>; def R2 : GPR< 2>; def R3 : GPR< 3>;
|
||||
def R4 : GPR< 4>; def R5 : GPR< 5>; def R6 : GPR< 6>; def R7 : GPR< 7>;
|
||||
def R8 : GPR< 8>; def R9 : GPR< 9>; def R10 : GPR<10>; def R11 : GPR<11>;
|
||||
def R12 : GPR<12>; def R13 : GPR<13>; def R14 : GPR<14>; def R15 : GPR<15>;
|
||||
def R16 : GPR<16>; def R17 : GPR<17>; def R18 : GPR<18>; def R19 : GPR<19>;
|
||||
def R20 : GPR<20>; def R21 : GPR<21>; def R22 : GPR<22>; def R23 : GPR<23>;
|
||||
def R24 : GPR<24>; def R25 : GPR<25>; def R26 : GPR<26>; def R27 : GPR<27>;
|
||||
def R28 : GPR<28>; def R29 : GPR<29>; def R30 : GPR<30>; def R31 : GPR<31>;
|
||||
|
||||
// Floating-point registers
|
||||
def F0 : FPR< 0>; def F1 : FPR< 1>; def F2 : FPR< 2>; def F3 : FPR< 3>;
|
||||
def F4 : FPR< 4>; def F5 : FPR< 5>; def F6 : FPR< 6>; def F7 : FPR< 7>;
|
||||
def F8 : FPR< 8>; def F9 : FPR< 9>; def F10 : FPR<10>; def F11 : FPR<11>;
|
||||
def F12 : FPR<12>; def F13 : FPR<13>; def F14 : FPR<14>; def F15 : FPR<15>;
|
||||
def F16 : FPR<16>; def F17 : FPR<17>; def F18 : FPR<18>; def F19 : FPR<19>;
|
||||
def F20 : FPR<20>; def F21 : FPR<21>; def F22 : FPR<22>; def F23 : FPR<23>;
|
||||
def F24 : FPR<24>; def F25 : FPR<25>; def F26 : FPR<26>; def F27 : FPR<27>;
|
||||
def F28 : FPR<28>; def F29 : FPR<29>; def F30 : FPR<30>; def F31 : FPR<31>;
|
||||
|
||||
// Condition registers
|
||||
def CR0 : CR<0>; def CR1 : CR<1>; def CR2 : CR<2>; def CR3 : CR<3>;
|
||||
def CR4 : CR<4>; def CR5 : CR<5>; def CR6 : CR<6>; def CR7 : CR<7>;
|
||||
|
||||
// Floating-point status and control register
|
||||
def FPSCR : SPR<0>;
|
||||
// fiXed-point Exception Register? :-)
|
||||
def XER : SPR<1>;
|
||||
// Link register
|
||||
def LR : SPR<2>;
|
||||
// Count register
|
||||
def CTR : SPR<3>;
|
||||
// These are the "time base" registers which are read-only in user mode.
|
||||
def TBL : SPR<4>;
|
||||
def TBU : SPR<5>;
|
||||
|
||||
/// Register classes: one for floats and another for non-floats.
|
||||
def GPRC : RegisterClass<i32, 4, [R0, R1, R2, R3, R4, R5, R6, R7,
|
||||
R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21,
|
||||
R22, R23, R24, R25, R26, R27, R28, R29, R30, R31]>;
|
||||
def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7,
|
||||
F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
|
||||
F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
|
||||
|
55
lib/Target/SparcV8/Makefile
Normal file
55
lib/Target/SparcV8/Makefile
Normal file
@ -0,0 +1,55 @@
|
||||
##===- lib/Target/SparcV8/Makefile -------------------------*- Makefile -*-===##
|
||||
#
|
||||
# The LLVM Compiler Infrastructure
|
||||
#
|
||||
# This file was developed by the LLVM research group and is distributed under
|
||||
# the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
#
|
||||
##===----------------------------------------------------------------------===##
|
||||
LEVEL = ../../..
|
||||
LIBRARYNAME = sparcv8
|
||||
include $(LEVEL)/Makefile.common
|
||||
|
||||
# Make sure that tblgen is run, first thing.
|
||||
$(SourceDepend): SparcV8GenRegisterInfo.h.inc SparcV8GenRegisterNames.inc \
|
||||
SparcV8GenRegisterInfo.inc SparcV8GenInstrNames.inc \
|
||||
SparcV8GenInstrInfo.inc SparcV8GenInstrSelector.inc
|
||||
|
||||
SparcV8GenRegisterNames.inc:: $(SourceDir)/SparcV8.td \
|
||||
$(SourceDir)/SparcV8Reg.td \
|
||||
$(SourceDir)/../Target.td $(TBLGEN)
|
||||
@echo "Building SparcV8.td register names with tblgen"
|
||||
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-enums -o $@
|
||||
|
||||
SparcV8GenRegisterInfo.h.inc:: $(SourceDir)/SparcV8.td \
|
||||
$(SourceDir)/SparcV8Reg.td \
|
||||
$(SourceDir)/../Target.td $(TBLGEN)
|
||||
@echo "Building SparcV8.td register information header with tblgen"
|
||||
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc-header -o $@
|
||||
|
||||
SparcV8GenRegisterInfo.inc:: $(SourceDir)/SparcV8.td \
|
||||
$(SourceDir)/SparcV8Reg.td \
|
||||
$(SourceDir)/../Target.td $(TBLGEN)
|
||||
@echo "Building SparcV8.td register information implementation with tblgen"
|
||||
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-register-desc -o $@
|
||||
|
||||
SparcV8GenInstrNames.inc:: $(SourceDir)/SparcV8.td \
|
||||
$(SourceDir)/SparcV8Instrs.td \
|
||||
$(SourceDir)/../Target.td $(TBLGEN)
|
||||
@echo "Building SparcV8.td instruction names with tblgen"
|
||||
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-enums -o $@
|
||||
|
||||
SparcV8GenInstrInfo.inc:: $(SourceDir)/SparcV8.td \
|
||||
$(SourceDir)/SparcV8Instrs.td \
|
||||
$(SourceDir)/../Target.td $(TBLGEN)
|
||||
@echo "Building SparcV8.td instruction information with tblgen"
|
||||
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-desc -o $@
|
||||
|
||||
SparcV8GenInstrSelector.inc:: $(SourceDir)/SparcV8.td \
|
||||
$(SourceDir)/SparcV8Instrs.td \
|
||||
$(SourceDir)/../Target.td $(TBLGEN)
|
||||
@echo "Building SparcV8.td instruction selector with tblgen"
|
||||
$(VERB) $(TBLGEN) -I $(BUILD_SRC_DIR) $< -gen-instr-selector -o $@
|
||||
|
||||
clean::
|
||||
$(VERB) rm -f *.inc
|
9
lib/Target/SparcV8/README.txt
Normal file
9
lib/Target/SparcV8/README.txt
Normal file
@ -0,0 +1,9 @@
|
||||
|
||||
SparcV8 backend skeleton
|
||||
------------------------
|
||||
|
||||
This directory will house a 32-bit SPARC V8 backend employing a expander-based
|
||||
instruction selector. Watch this space for more news coming soon!
|
||||
|
||||
$Date$
|
||||
|
42
lib/Target/SparcV8/SparcV8.h
Normal file
42
lib/Target/SparcV8/SparcV8.h
Normal file
@ -0,0 +1,42 @@
|
||||
//===-- SparcV8.h - Top-level interface for SparcV8 representation -*- C++ -*-//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file contains the entry points for global functions defined in the LLVM
|
||||
// SparcV8 back-end.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef TARGET_SPARCV8_H
|
||||
#define TARGET_SPARCV8_H
|
||||
|
||||
#include <iosfwd>
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class FunctionPass;
|
||||
class TargetMachine;
|
||||
|
||||
// Here is where you would define factory methods for sparcv8-specific
|
||||
// passes. For example:
|
||||
// FunctionPass *createSparcV8SimpleInstructionSelector (TargetMachine &TM);
|
||||
// FunctionPass *createSparcV8CodePrinterPass(std::ostream &OS,
|
||||
// TargetMachine &TM);
|
||||
|
||||
} // end namespace llvm;
|
||||
|
||||
// Defines symbolic names for SparcV8 registers. This defines a mapping from
|
||||
// register name to register number.
|
||||
//
|
||||
#include "SparcV8GenRegisterNames.inc"
|
||||
|
||||
// Defines symbolic names for the SparcV8 instructions.
|
||||
//
|
||||
#include "SparcV8GenInstrNames.inc"
|
||||
|
||||
#endif
|
41
lib/Target/SparcV8/SparcV8.td
Normal file
41
lib/Target/SparcV8/SparcV8.td
Normal file
@ -0,0 +1,41 @@
|
||||
//===- SparcV8.td - Describe the SparcV8 Target Machine ---------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
// Get the target-independent interfaces which we are implementing...
|
||||
//
|
||||
include "../Target.td"
|
||||
|
||||
//===----------------------------------------------------------------------===//
|
||||
// Register File Description
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
include "SparcV8Reg.td"
|
||||
include "SparcV8Instrs.td"
|
||||
|
||||
def SparcV8InstrInfo : InstrInfo {
|
||||
let PHIInst = PHI;
|
||||
}
|
||||
|
||||
def SparcV8 : Target {
|
||||
// Pointers are 32-bits in size.
|
||||
let PointerType = i32;
|
||||
|
||||
// According to the Mach-O Runtime ABI, these regs are nonvolatile across
|
||||
// calls:
|
||||
let CalleeSavedRegisters = [R1, R13, R14, R15, R16, R17, R18, R19,
|
||||
R20, R21, R22, R23, R24, R25, R26, R27, R28, R29, R30, R31, F14, F15,
|
||||
F16, F17, F18, F19, F20, F21, F22, F23, F24, F25, F26, F27, F28, F29,
|
||||
F30, F31, CR2, CR3, CR4];
|
||||
|
||||
// Pull in Instruction Info:
|
||||
let InstructionSet = SparcV8InstrInfo;
|
||||
}
|
43
lib/Target/SparcV8/SparcV8CodeEmitter.cpp
Normal file
43
lib/Target/SparcV8/SparcV8CodeEmitter.cpp
Normal file
@ -0,0 +1,43 @@
|
||||
//===-- SparcV8CodeEmitter.cpp - JIT Code Emitter for SparcV8 -----*- C++ -*-=//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "SparcV8TargetMachine.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
/// addPassesToEmitMachineCode - Add passes to the specified pass manager to get
|
||||
/// machine code emitted. This uses a MachineCodeEmitter object to handle
|
||||
/// actually outputting the machine code and resolving things like the address
|
||||
/// of functions. This method should returns true if machine code emission is
|
||||
/// not supported.
|
||||
///
|
||||
bool SparcV8TargetMachine::addPassesToEmitMachineCode(FunctionPassManager &PM,
|
||||
MachineCodeEmitter &MCE) {
|
||||
return true;
|
||||
// It should go something like this:
|
||||
// PM.add(new Emitter(MCE)); // Machine code emitter pass for SparcV8
|
||||
// Delete machine code for this function after emitting it:
|
||||
// PM.add(createMachineCodeDeleter());
|
||||
}
|
||||
|
||||
void *SparcV8JITInfo::getJITStubForFunction(Function *F,
|
||||
MachineCodeEmitter &MCE) {
|
||||
assert (0 && "SparcV8JITInfo::getJITStubForFunction not implemented");
|
||||
return 0;
|
||||
}
|
||||
|
||||
void SparcV8JITInfo::replaceMachineCodeForFunction (void *Old, void *New) {
|
||||
assert (0 && "SparcV8JITInfo::replaceMachineCodeForFunction not implemented");
|
||||
}
|
||||
|
||||
} // end llvm namespace
|
||||
|
42
lib/Target/SparcV8/SparcV8InstrInfo.cpp
Normal file
42
lib/Target/SparcV8/SparcV8InstrInfo.cpp
Normal file
@ -0,0 +1,42 @@
|
||||
//===- SparcV8InstrInfo.cpp - SparcV8 Instruction Information ---*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file contains the SparcV8 implementation of the TargetInstrInfo class.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "SparcV8InstrInfo.h"
|
||||
#include "llvm/CodeGen/MachineInstrBuilder.h"
|
||||
#include "SparcV8GenInstrInfo.inc"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
SparcV8InstrInfo::SparcV8InstrInfo()
|
||||
: TargetInstrInfo(SparcV8Insts,
|
||||
sizeof(SparcV8Insts)/sizeof(SparcV8Insts[0]), 0) {
|
||||
}
|
||||
|
||||
// createNOPinstr - returns the target's implementation of NOP, which is
|
||||
// usually a pseudo-instruction, implemented by a degenerate version of
|
||||
// another instruction.
|
||||
//
|
||||
MachineInstr* SparcV8InstrInfo::createNOPinstr() const {
|
||||
return 0;
|
||||
}
|
||||
|
||||
/// isNOPinstr - not having a special NOP opcode, we need to know if a given
|
||||
/// instruction is interpreted as an `official' NOP instr, i.e., there may be
|
||||
/// more than one way to `do nothing' but only one canonical way to slack off.
|
||||
//
|
||||
bool SparcV8InstrInfo::isNOPinstr(const MachineInstr &MI) const {
|
||||
return false;
|
||||
}
|
||||
|
||||
} // end namespace llvm
|
||||
|
48
lib/Target/SparcV8/SparcV8InstrInfo.h
Normal file
48
lib/Target/SparcV8/SparcV8InstrInfo.h
Normal file
@ -0,0 +1,48 @@
|
||||
//===- SparcV8InstrInfo.h - SparcV8 Instruction Information -----*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file contains the SparcV8 implementation of the TargetInstrInfo class.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef SPARCV8INSTRUCTIONINFO_H
|
||||
#define SPARCV8INSTRUCTIONINFO_H
|
||||
|
||||
#include "llvm/Target/TargetInstrInfo.h"
|
||||
#include "SparcV8RegisterInfo.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class SparcV8InstrInfo : public TargetInstrInfo {
|
||||
const SparcV8RegisterInfo RI;
|
||||
public:
|
||||
SparcV8InstrInfo();
|
||||
|
||||
/// getRegisterInfo - TargetInstrInfo is a superset of MRegister info. As
|
||||
/// such, whenever a client has an instance of instruction info, it should
|
||||
/// always be able to get register info as well (through this method).
|
||||
///
|
||||
virtual const MRegisterInfo &getRegisterInfo() const { return RI; }
|
||||
|
||||
/// createNOPinstr - returns the target's implementation of NOP, which is
|
||||
/// usually a pseudo-instruction, implemented by a degenerate version of
|
||||
/// another instruction.
|
||||
///
|
||||
MachineInstr* createNOPinstr() const;
|
||||
|
||||
/// isNOPinstr - not having a special NOP opcode, we need to know if a given
|
||||
/// instruction is interpreted as an `official' NOP instr, i.e., there may be
|
||||
/// more than one way to `do nothing' but only one canonical way to slack off.
|
||||
///
|
||||
bool isNOPinstr(const MachineInstr &MI) const;
|
||||
};
|
||||
|
||||
}
|
||||
|
||||
#endif
|
46
lib/Target/SparcV8/SparcV8Instrs.td
Normal file
46
lib/Target/SparcV8/SparcV8Instrs.td
Normal file
@ -0,0 +1,46 @@
|
||||
//===- SparcV8InstrInfo.td - Describe the SparcV8 Instruction Set -*- C++ -*-=//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class Format<bits<4> val> {
|
||||
bits<4> Value = val;
|
||||
}
|
||||
|
||||
// All of the SparcV8 instruction formats, plus a pseudo-instruction format:
|
||||
def Pseudo : Format<0>;
|
||||
def IForm : Format<1>;
|
||||
def BForm : Format<2>;
|
||||
def SCForm : Format<3>;
|
||||
def DForm : Format<4>;
|
||||
def XForm : Format<5>;
|
||||
def XLForm : Format<6>;
|
||||
def XFXForm : Format<7>;
|
||||
def XFLForm : Format<8>;
|
||||
def XOForm : Format<9>;
|
||||
def AForm : Format<10>;
|
||||
def MForm : Format<11>;
|
||||
|
||||
class PPCInst<string nm, bits<6> opcd, Format f> : Instruction {
|
||||
let Namespace = "SparcV8";
|
||||
|
||||
let Name = nm;
|
||||
bits<6> Opcode = opcd;
|
||||
Format Form = f;
|
||||
bits<4> FormBits = Form.Value;
|
||||
}
|
||||
|
||||
// Pseudo-instructions:
|
||||
def PHI : PPCInst<"PHI", 0, Pseudo>; // PHI node...
|
||||
def NOP : PPCInst<"NOP", 0, Pseudo>; // No-op
|
||||
def ADJCALLSTACKDOWN : PPCInst<"ADJCALLSTACKDOWN", 0, Pseudo>;
|
||||
def ADJCALLSTACKUP : PPCInst<"ADJCALLSTACKUP", 0, Pseudo>;
|
||||
|
||||
|
49
lib/Target/SparcV8/SparcV8JITInfo.h
Normal file
49
lib/Target/SparcV8/SparcV8JITInfo.h
Normal file
@ -0,0 +1,49 @@
|
||||
//===- SparcV8JITInfo.h - SparcV8 impl. of the JIT interface ----*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file contains the SparcV8 implementation of the TargetJITInfo class.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef SPARCV8JITINFO_H
|
||||
#define SPARCV8JITINFO_H
|
||||
|
||||
#include "llvm/Target/TargetJITInfo.h"
|
||||
|
||||
namespace llvm {
|
||||
class TargetMachine;
|
||||
class IntrinsicLowering;
|
||||
|
||||
class SparcV8JITInfo : public TargetJITInfo {
|
||||
TargetMachine &TM;
|
||||
public:
|
||||
SparcV8JITInfo(TargetMachine &tm) : TM(tm) {}
|
||||
|
||||
/// addPassesToJITCompile - Add passes to the specified pass manager to
|
||||
/// implement a fast dynamic compiler for this target. Return true if this
|
||||
/// is not supported for this target.
|
||||
///
|
||||
virtual void addPassesToJITCompile(FunctionPassManager &PM);
|
||||
|
||||
/// replaceMachineCodeForFunction - Make it so that calling the function
|
||||
/// whose machine code is at OLD turns into a call to NEW, perhaps by
|
||||
/// overwriting OLD with a branch to NEW. This is used for self-modifying
|
||||
/// code.
|
||||
///
|
||||
virtual void replaceMachineCodeForFunction(void *Old, void *New);
|
||||
|
||||
/// getJITStubForFunction - Create or return a stub for the specified
|
||||
/// function. This stub acts just like the specified function, except that
|
||||
/// it allows the "address" of the function to be taken without having to
|
||||
/// generate code for it.
|
||||
virtual void *getJITStubForFunction(Function *F, MachineCodeEmitter &MCE);
|
||||
};
|
||||
}
|
||||
|
||||
#endif
|
82
lib/Target/SparcV8/SparcV8Reg.td
Normal file
82
lib/Target/SparcV8/SparcV8Reg.td
Normal file
@ -0,0 +1,82 @@
|
||||
//===- SparcV8Reg.td - Describe the SparcV8 Register File -------*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class PPCReg : Register {
|
||||
let Namespace = "SparcV8";
|
||||
}
|
||||
|
||||
// We identify all our registers with a 5-bit ID, for consistency's sake.
|
||||
|
||||
// GPR - One of the 32 32-bit general-purpose registers
|
||||
class GPR<bits<5> num> : PPCReg {
|
||||
field bits<5> Num = num;
|
||||
}
|
||||
|
||||
// SPR - One of the 32-bit special-purpose registers
|
||||
class SPR<bits<5> num> : PPCReg {
|
||||
field bits<5> Num = num;
|
||||
}
|
||||
|
||||
// FPR - One of the 32 64-bit floating-point registers
|
||||
class FPR<bits<5> num> : PPCReg {
|
||||
field bits<5> Num = num;
|
||||
}
|
||||
|
||||
// CR - One of the 8 4-bit condition registers
|
||||
class CR<bits<5> num> : PPCReg {
|
||||
field bits<5> Num = num;
|
||||
}
|
||||
|
||||
// General-purpose registers
|
||||
def R0 : GPR< 0>; def R1 : GPR< 1>; def R2 : GPR< 2>; def R3 : GPR< 3>;
|
||||
def R4 : GPR< 4>; def R5 : GPR< 5>; def R6 : GPR< 6>; def R7 : GPR< 7>;
|
||||
def R8 : GPR< 8>; def R9 : GPR< 9>; def R10 : GPR<10>; def R11 : GPR<11>;
|
||||
def R12 : GPR<12>; def R13 : GPR<13>; def R14 : GPR<14>; def R15 : GPR<15>;
|
||||
def R16 : GPR<16>; def R17 : GPR<17>; def R18 : GPR<18>; def R19 : GPR<19>;
|
||||
def R20 : GPR<20>; def R21 : GPR<21>; def R22 : GPR<22>; def R23 : GPR<23>;
|
||||
def R24 : GPR<24>; def R25 : GPR<25>; def R26 : GPR<26>; def R27 : GPR<27>;
|
||||
def R28 : GPR<28>; def R29 : GPR<29>; def R30 : GPR<30>; def R31 : GPR<31>;
|
||||
|
||||
// Floating-point registers
|
||||
def F0 : FPR< 0>; def F1 : FPR< 1>; def F2 : FPR< 2>; def F3 : FPR< 3>;
|
||||
def F4 : FPR< 4>; def F5 : FPR< 5>; def F6 : FPR< 6>; def F7 : FPR< 7>;
|
||||
def F8 : FPR< 8>; def F9 : FPR< 9>; def F10 : FPR<10>; def F11 : FPR<11>;
|
||||
def F12 : FPR<12>; def F13 : FPR<13>; def F14 : FPR<14>; def F15 : FPR<15>;
|
||||
def F16 : FPR<16>; def F17 : FPR<17>; def F18 : FPR<18>; def F19 : FPR<19>;
|
||||
def F20 : FPR<20>; def F21 : FPR<21>; def F22 : FPR<22>; def F23 : FPR<23>;
|
||||
def F24 : FPR<24>; def F25 : FPR<25>; def F26 : FPR<26>; def F27 : FPR<27>;
|
||||
def F28 : FPR<28>; def F29 : FPR<29>; def F30 : FPR<30>; def F31 : FPR<31>;
|
||||
|
||||
// Condition registers
|
||||
def CR0 : CR<0>; def CR1 : CR<1>; def CR2 : CR<2>; def CR3 : CR<3>;
|
||||
def CR4 : CR<4>; def CR5 : CR<5>; def CR6 : CR<6>; def CR7 : CR<7>;
|
||||
|
||||
// Floating-point status and control register
|
||||
def FPSCR : SPR<0>;
|
||||
// fiXed-point Exception Register? :-)
|
||||
def XER : SPR<1>;
|
||||
// Link register
|
||||
def LR : SPR<2>;
|
||||
// Count register
|
||||
def CTR : SPR<3>;
|
||||
// These are the "time base" registers which are read-only in user mode.
|
||||
def TBL : SPR<4>;
|
||||
def TBU : SPR<5>;
|
||||
|
||||
/// Register classes: one for floats and another for non-floats.
|
||||
def GPRC : RegisterClass<i32, 4, [R0, R1, R2, R3, R4, R5, R6, R7,
|
||||
R8, R9, R10, R11, R12, R13, R14, R15, R16, R17, R18, R19, R20, R21,
|
||||
R22, R23, R24, R25, R26, R27, R28, R29, R30, R31]>;
|
||||
def FPRC : RegisterClass<f64, 8, [F0, F1, F2, F3, F4, F5, F6, F7,
|
||||
F8, F9, F10, F11, F12, F13, F14, F15, F16, F17, F18, F19, F20, F21,
|
||||
F22, F23, F24, F25, F26, F27, F28, F29, F30, F31]>;
|
||||
|
99
lib/Target/SparcV8/SparcV8RegisterInfo.cpp
Normal file
99
lib/Target/SparcV8/SparcV8RegisterInfo.cpp
Normal file
@ -0,0 +1,99 @@
|
||||
//===- SparcV8RegisterInfo.cpp - SparcV8 Register Information ---*- C++ -*-===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file contains the SparcV8 implementation of the MRegisterInfo class.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "SparcV8.h"
|
||||
#include "SparcV8RegisterInfo.h"
|
||||
#include "llvm/Type.h"
|
||||
using namespace llvm;
|
||||
|
||||
SparcV8RegisterInfo::SparcV8RegisterInfo()
|
||||
: SparcV8GenRegisterInfo(SparcV8::ADJCALLSTACKDOWN,
|
||||
SparcV8::ADJCALLSTACKUP) {}
|
||||
|
||||
int SparcV8RegisterInfo::storeRegToStackSlot(
|
||||
MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MBBI,
|
||||
unsigned SrcReg, int FrameIdx,
|
||||
const TargetRegisterClass *RC) const
|
||||
{
|
||||
abort();
|
||||
return -1;
|
||||
}
|
||||
|
||||
int SparcV8RegisterInfo::loadRegFromStackSlot(
|
||||
MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MBBI,
|
||||
unsigned DestReg, int FrameIdx,
|
||||
const TargetRegisterClass *RC) const
|
||||
{
|
||||
abort();
|
||||
return -1;
|
||||
}
|
||||
|
||||
int SparcV8RegisterInfo::copyRegToReg(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MBBI,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
const TargetRegisterClass *RC) const {
|
||||
abort();
|
||||
return -1;
|
||||
}
|
||||
|
||||
void SparcV8RegisterInfo::
|
||||
eliminateCallFramePseudoInstr(MachineFunction &MF, MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator I) const {
|
||||
abort();
|
||||
}
|
||||
|
||||
void
|
||||
SparcV8RegisterInfo::eliminateFrameIndex(MachineFunction &MF,
|
||||
MachineBasicBlock::iterator II) const {
|
||||
abort();
|
||||
}
|
||||
|
||||
void SparcV8RegisterInfo::processFunctionBeforeFrameFinalized(
|
||||
MachineFunction &MF) const {
|
||||
abort();
|
||||
}
|
||||
|
||||
void SparcV8RegisterInfo::emitPrologue(MachineFunction &MF) const {
|
||||
abort();
|
||||
}
|
||||
|
||||
void SparcV8RegisterInfo::emitEpilogue(MachineFunction &MF,
|
||||
MachineBasicBlock &MBB) const {
|
||||
abort();
|
||||
}
|
||||
|
||||
|
||||
#include "SparcV8GenRegisterInfo.inc"
|
||||
|
||||
const TargetRegisterClass*
|
||||
SparcV8RegisterInfo::getRegClassForType(const Type* Ty) const {
|
||||
switch (Ty->getPrimitiveID()) {
|
||||
case Type::LongTyID:
|
||||
case Type::ULongTyID: assert(0 && "Long values can't fit in registers!");
|
||||
default: assert(0 && "Invalid type to getClass!");
|
||||
case Type::BoolTyID:
|
||||
case Type::SByteTyID:
|
||||
case Type::UByteTyID:
|
||||
case Type::ShortTyID:
|
||||
case Type::UShortTyID:
|
||||
case Type::IntTyID:
|
||||
case Type::UIntTyID:
|
||||
case Type::PointerTyID: return &GPRCInstance;
|
||||
|
||||
case Type::FloatTyID:
|
||||
case Type::DoubleTyID: return &FPRCInstance;
|
||||
}
|
||||
}
|
||||
|
58
lib/Target/SparcV8/SparcV8RegisterInfo.h
Normal file
58
lib/Target/SparcV8/SparcV8RegisterInfo.h
Normal file
@ -0,0 +1,58 @@
|
||||
//===- SparcV8RegisterInfo.h - SparcV8 Register Information Impl -*- C++ -*-==//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file contains the SparcV8 implementation of the MRegisterInfo class.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef SPARCV8REGISTERINFO_H
|
||||
#define SPARCV8REGISTERINFO_H
|
||||
|
||||
#include "llvm/Target/MRegisterInfo.h"
|
||||
#include "SparcV8GenRegisterInfo.h.inc"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class Type;
|
||||
|
||||
struct SparcV8RegisterInfo : public SparcV8GenRegisterInfo {
|
||||
SparcV8RegisterInfo();
|
||||
const TargetRegisterClass* getRegClassForType(const Type* Ty) const;
|
||||
|
||||
/// Code Generation virtual methods...
|
||||
int storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MBBI,
|
||||
unsigned SrcReg, int FrameIndex,
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
int loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator MBBI,
|
||||
unsigned DestReg, int FrameIndex,
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
int copyRegToReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
||||
unsigned DestReg, unsigned SrcReg,
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
void eliminateCallFramePseudoInstr(MachineFunction &MF,
|
||||
MachineBasicBlock &MBB,
|
||||
MachineBasicBlock::iterator I) const;
|
||||
|
||||
void eliminateFrameIndex(MachineFunction &MF,
|
||||
MachineBasicBlock::iterator II) const;
|
||||
|
||||
void processFunctionBeforeFrameFinalized(MachineFunction &MF) const;
|
||||
|
||||
void emitPrologue(MachineFunction &MF) const;
|
||||
void emitEpilogue(MachineFunction &MF, MachineBasicBlock &MBB) const;
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
#endif
|
61
lib/Target/SparcV8/SparcV8TargetMachine.cpp
Normal file
61
lib/Target/SparcV8/SparcV8TargetMachine.cpp
Normal file
@ -0,0 +1,61 @@
|
||||
//===-- SparcV8TargetMachine.cpp - Define TargetMachine for SparcV8 -------===//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#include "SparcV8TargetMachine.h"
|
||||
#include "SparcV8.h"
|
||||
#include "llvm/Module.h"
|
||||
#include "llvm/PassManager.h"
|
||||
#include "llvm/Target/TargetMachineImpls.h"
|
||||
#include "llvm/CodeGen/MachineFunction.h"
|
||||
#include "llvm/CodeGen/Passes.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
// allocateSparcV8TargetMachine - Allocate and return a subclass of
|
||||
// TargetMachine that implements the SparcV8 backend.
|
||||
//
|
||||
TargetMachine *allocateSparcV8TargetMachine(const Module &M,
|
||||
IntrinsicLowering *IL) {
|
||||
return new SparcV8TargetMachine(M, IL);
|
||||
}
|
||||
|
||||
/// SparcV8TargetMachine ctor - Create an ILP32 architecture model
|
||||
///
|
||||
SparcV8TargetMachine::SparcV8TargetMachine(const Module &M,
|
||||
IntrinsicLowering *IL)
|
||||
: TargetMachine("SparcV8", IL, true, 4, 4, 4, 4, 4),
|
||||
FrameInfo(TargetFrameInfo::StackGrowsDown, 8, 4), JITInfo(*this) {
|
||||
}
|
||||
|
||||
/// addPassesToEmitAssembly - Add passes to the specified pass manager
|
||||
/// to implement a static compiler for this target.
|
||||
///
|
||||
bool SparcV8TargetMachine::addPassesToEmitAssembly(PassManager &PM,
|
||||
std::ostream &Out) {
|
||||
// <insert instruction selector passes here>
|
||||
PM.add(createRegisterAllocator());
|
||||
PM.add(createPrologEpilogCodeInserter());
|
||||
// <insert assembly code output passes here>
|
||||
PM.add(createMachineCodeDeleter());
|
||||
return true; // change to `return false' when this actually works.
|
||||
}
|
||||
|
||||
/// addPassesToJITCompile - Add passes to the specified pass manager to
|
||||
/// implement a fast dynamic compiler for this target.
|
||||
///
|
||||
void SparcV8JITInfo::addPassesToJITCompile(FunctionPassManager &PM) {
|
||||
// <insert instruction selector passes here>
|
||||
PM.add(createRegisterAllocator());
|
||||
PM.add(createPrologEpilogCodeInserter());
|
||||
}
|
||||
|
||||
} // end namespace llvm
|
61
lib/Target/SparcV8/SparcV8TargetMachine.h
Normal file
61
lib/Target/SparcV8/SparcV8TargetMachine.h
Normal file
@ -0,0 +1,61 @@
|
||||
//===-- SparcV8TargetMachine.h - Define TargetMachine for SparcV8 -*- C++ -*-=//
|
||||
//
|
||||
// The LLVM Compiler Infrastructure
|
||||
//
|
||||
// This file was developed by the LLVM research group and is distributed under
|
||||
// the University of Illinois Open Source License. See LICENSE.TXT for details.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
//
|
||||
// This file declares the SparcV8 specific subclass of TargetMachine.
|
||||
//
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
#ifndef SPARCV8TARGETMACHINE_H
|
||||
#define SPARCV8TARGETMACHINE_H
|
||||
|
||||
#include "llvm/Target/TargetMachine.h"
|
||||
#include "llvm/Target/TargetFrameInfo.h"
|
||||
#include "llvm/PassManager.h"
|
||||
#include "SparcV8InstrInfo.h"
|
||||
#include "SparcV8JITInfo.h"
|
||||
|
||||
namespace llvm {
|
||||
|
||||
class IntrinsicLowering;
|
||||
|
||||
class SparcV8TargetMachine : public TargetMachine {
|
||||
SparcV8InstrInfo InstrInfo;
|
||||
TargetFrameInfo FrameInfo;
|
||||
SparcV8JITInfo JITInfo;
|
||||
public:
|
||||
SparcV8TargetMachine(const Module &M, IntrinsicLowering *IL);
|
||||
|
||||
virtual const SparcV8InstrInfo &getInstrInfo() const { return InstrInfo; }
|
||||
virtual const TargetFrameInfo &getFrameInfo() const { return FrameInfo; }
|
||||
virtual const MRegisterInfo *getRegisterInfo() const {
|
||||
return &InstrInfo.getRegisterInfo();
|
||||
}
|
||||
virtual TargetJITInfo *getJITInfo() {
|
||||
return &JITInfo;
|
||||
}
|
||||
|
||||
virtual const TargetSchedInfo &getSchedInfo() const { abort(); }
|
||||
virtual const TargetRegInfo &getRegInfo() const { abort(); }
|
||||
virtual const TargetCacheInfo &getCacheInfo() const { abort(); }
|
||||
|
||||
/// addPassesToEmitMachineCode - Add passes to the specified pass manager to
|
||||
/// get machine code emitted. This uses a MachineCodeEmitter object to handle
|
||||
/// actually outputting the machine code and resolving things like the address
|
||||
/// of functions. This method should returns true if machine code emission is
|
||||
/// not supported.
|
||||
///
|
||||
virtual bool addPassesToEmitMachineCode(FunctionPassManager &PM,
|
||||
MachineCodeEmitter &MCE);
|
||||
|
||||
virtual bool addPassesToEmitAssembly(PassManager &PM, std::ostream &Out);
|
||||
};
|
||||
|
||||
} // end namespace llvm
|
||||
|
||||
#endif
|
Loading…
Reference in New Issue
Block a user