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R600: Add IsExport bit to TableGen instruction definitions

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Tested-by: Aaron Watry <awatry@gmail.com>

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@188516 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tom Stellard
2013-08-16 01:11:51 +00:00
parent e560d526a1
commit e7ac2ed1c2
6 changed files with 16 additions and 10 deletions
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3
lib/Target/R600/R600Instructions.td
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@@ -278,6 +278,7 @@ class EG_CF_RAT <bits <8> cfinst, bits <6> ratinst, bits<4> ratid, bits<4> mask,
let Inst{31-0} = Word0;
let Inst{63-32} = Word1;
let IsExport = 1;
}
@@ -551,6 +552,7 @@ class ExportSwzInst : InstR600ISA<(
let elem_size = 3;
let Inst{31-0} = Word0;
let Inst{63-32} = Word1;
let IsExport = 1;
}
} // End usesCustomInserter = 1
@@ -564,6 +566,7 @@ class ExportBufInst : InstR600ISA<(
let elem_size = 0;
let Inst{31-0} = Word0;
let Inst{63-32} = Word1;
let IsExport = 1;
}
//===----------------------------------------------------------------------===//