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[FastISel][AArch64] Use the correct register class for branches.
Also constrain the register class for branches. This fixes rdar://problem/18181496. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@216804 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2182,15 +2182,16 @@ bool AArch64FastISel::FastLowerCall(CallLoweringInfo &CLI) {
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// Issue the call.
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MachineInstrBuilder MIB;
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if (CM == CodeModel::Small) {
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unsigned CallOpc = Addr.getReg() ? AArch64::BLR : AArch64::BL;
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MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, TII.get(CallOpc));
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const MCInstrDesc &II = TII.get(Addr.getReg() ? AArch64::BLR : AArch64::BL);
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MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II);
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if (SymName)
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MIB.addExternalSymbol(SymName, 0);
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else if (Addr.getGlobalValue())
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MIB.addGlobalAddress(Addr.getGlobalValue(), 0, 0);
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else if (Addr.getReg())
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MIB.addReg(Addr.getReg());
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else
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else if (Addr.getReg()) {
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unsigned Reg = constrainOperandRegClass(II, Addr.getReg(), 0);
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MIB.addReg(Reg);
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} else
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return false;
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} else {
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unsigned CallReg = 0;
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@ -2214,8 +2215,9 @@ bool AArch64FastISel::FastLowerCall(CallLoweringInfo &CLI) {
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if (!CallReg)
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return false;
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MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc,
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TII.get(AArch64::BLR)).addReg(CallReg);
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const MCInstrDesc &II = TII.get(AArch64::BLR);
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CallReg = constrainOperandRegClass(II, CallReg, 0);
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MIB = BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DbgLoc, II).addReg(CallReg);
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}
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// Add implicit physical register uses to the call.
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@ -252,3 +252,18 @@ define void @call_arguments9(i8 %a1, i16 %a2, i32 %a3, i64 %a4, float %a5, doubl
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; CHECK-LABEL: call_arguments9
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ret void
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}
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; Test that we use the correct register class for the branch.
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define void @call_blr(i64 %Fn, i1 %c) {
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; CHECK-LABEL: call_blr
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; CHECK: blr
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br i1 %c, label %bb1, label %bb2
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bb1:
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%1 = inttoptr i64 %Fn to void (i64)*
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br label %bb2
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bb2:
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%2 = phi void (i64)* [ %1, %bb1 ], [ undef, %0 ]
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call void %2(i64 1)
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ret void
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}
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