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https://github.com/c64scene-ar/llvm-6502.git
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Framework for atomic binary operations. The emitter for the pseudo instructions
just issues an error for the moment. The front end won't yet generate these intrinsics for ARM, so this is behind the scenes until complete. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@91200 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Jim Grosbach
parent
73a1b67cb9
commit
e801dc4a7b
@ -42,6 +42,7 @@
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#include "llvm/Support/CommandLine.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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#include <sstream>
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using namespace llvm;
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@ -3043,8 +3044,9 @@ void ARMTargetLowering::ReplaceNodeResults(SDNode *N,
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//===----------------------------------------------------------------------===//
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MachineBasicBlock *
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ARMTargetLowering::EmitAtomicCmpSwap(unsigned Size, MachineInstr *MI,
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MachineBasicBlock *BB) const {
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ARMTargetLowering::EmitAtomicCmpSwap(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned Size) const {
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unsigned dest = MI->getOperand(0).getReg();
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unsigned ptr = MI->getOperand(1).getReg();
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unsigned oldval = MI->getOperand(2).getReg();
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@ -3113,6 +3115,16 @@ ARMTargetLowering::EmitAtomicCmpSwap(unsigned Size, MachineInstr *MI,
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return BB;
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}
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MachineBasicBlock *
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ARMTargetLowering::EmitAtomicBinary(MachineInstr *MI, MachineBasicBlock *BB,
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unsigned Size, unsigned BinOpcode) const {
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std::string msg;
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raw_string_ostream Msg(msg);
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Msg << "Cannot yet emit: ";
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MI->print(Msg);
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llvm_report_error(Msg.str());
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}
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MachineBasicBlock *
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ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MachineBasicBlock *BB,
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@ -3124,12 +3136,37 @@ ARMTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI,
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MI->dump();
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llvm_unreachable("Unexpected instr type to insert");
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case ARM::ATOMIC_LOAD_ADD_I8: return EmitAtomicBinary(MI, BB, 1, ARM::ADDrr);
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case ARM::ATOMIC_LOAD_ADD_I16: return EmitAtomicBinary(MI, BB, 2, ARM::ADDrr);
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case ARM::ATOMIC_LOAD_ADD_I32: return EmitAtomicBinary(MI, BB, 4, ARM::ADDrr);
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case ARM::ATOMIC_LOAD_AND_I8: return EmitAtomicBinary(MI, BB, 1, ARM::ANDrr);
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case ARM::ATOMIC_LOAD_AND_I16: return EmitAtomicBinary(MI, BB, 2, ARM::ANDrr);
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case ARM::ATOMIC_LOAD_AND_I32: return EmitAtomicBinary(MI, BB, 4, ARM::ANDrr);
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case ARM::ATOMIC_LOAD_OR_I8: return EmitAtomicBinary(MI, BB, 1, ARM::ORRrr);
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case ARM::ATOMIC_LOAD_OR_I16: return EmitAtomicBinary(MI, BB, 2, ARM::ORRrr);
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case ARM::ATOMIC_LOAD_OR_I32: return EmitAtomicBinary(MI, BB, 4, ARM::ORRrr);
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case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(1, MI, BB);
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case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(2, MI, BB);
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case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(4, MI, BB);
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case ARM::ATOMIC_LOAD_XOR_I8: return EmitAtomicBinary(MI, BB, 1, ARM::EORrr);
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case ARM::ATOMIC_LOAD_XOR_I16: return EmitAtomicBinary(MI, BB, 2, ARM::EORrr);
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case ARM::ATOMIC_LOAD_XOR_I32: return EmitAtomicBinary(MI, BB, 4, ARM::EORrr);
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case ARM::ATOMIC_LOAD_NAND_I8: return EmitAtomicBinary(MI, BB, 1, ARM::BICrr);
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case ARM::ATOMIC_LOAD_NAND_I16:return EmitAtomicBinary(MI, BB, 2, ARM::BICrr);
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case ARM::ATOMIC_LOAD_NAND_I32:return EmitAtomicBinary(MI, BB, 4, ARM::BICrr);
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case ARM::ATOMIC_LOAD_SUB_I8: return EmitAtomicBinary(MI, BB, 1, ARM::SUBrr);
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case ARM::ATOMIC_LOAD_SUB_I16: return EmitAtomicBinary(MI, BB, 2, ARM::SUBrr);
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case ARM::ATOMIC_LOAD_SUB_I32: return EmitAtomicBinary(MI, BB, 4, ARM::SUBrr);
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case ARM::ATOMIC_SWAP_I8: return EmitAtomicBinary(MI, BB, 1, 0);
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case ARM::ATOMIC_SWAP_I16: return EmitAtomicBinary(MI, BB, 2, 0);
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case ARM::ATOMIC_SWAP_I32: return EmitAtomicBinary(MI, BB, 4, 0);
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case ARM::ATOMIC_CMP_SWAP_I8: return EmitAtomicCmpSwap(MI, BB, 1);
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case ARM::ATOMIC_CMP_SWAP_I16: return EmitAtomicCmpSwap(MI, BB, 2);
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case ARM::ATOMIC_CMP_SWAP_I32: return EmitAtomicCmpSwap(MI, BB, 4);
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case ARM::tMOVCCr_pseudo: {
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// To "insert" a SELECT_CC instruction, we actually have to insert the
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@ -332,8 +332,13 @@ namespace llvm {
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SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
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SDValue &ARMCC, SelectionDAG &DAG, DebugLoc dl);
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MachineBasicBlock *EmitAtomicCmpSwap(unsigned Size, MachineInstr *MI,
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MachineBasicBlock *BB) const;
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MachineBasicBlock *EmitAtomicCmpSwap(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned Size) const;
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MachineBasicBlock *EmitAtomicBinary(MachineInstr *MI,
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MachineBasicBlock *BB,
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unsigned Size,
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unsigned BinOpcode) const;
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};
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}
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@ -1597,18 +1597,107 @@ def Int_SyncBarrierV7 : AI<(outs), (ins),
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}
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let usesCustomInserter = 1 in {
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def ATOMIC_CMP_SWAP_I8 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
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"${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!",
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[(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
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def ATOMIC_CMP_SWAP_I16 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
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"${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!",
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[(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
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def ATOMIC_CMP_SWAP_I32 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
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"${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
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[(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
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let Uses = [CPSR] in {
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def ATOMIC_LOAD_ADD_I8 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_ADD_I8 PSEUDO!",
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[(set GPR:$dst, (atomic_load_add_8 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_SUB_I8 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_SUB_I8 PSEUDO!",
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[(set GPR:$dst, (atomic_load_sub_8 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_AND_I8 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_AND_I8 PSEUDO!",
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[(set GPR:$dst, (atomic_load_and_8 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_OR_I8 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_OR_I8 PSEUDO!",
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[(set GPR:$dst, (atomic_load_or_8 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_XOR_I8 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_XOR_I8 PSEUDO!",
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[(set GPR:$dst, (atomic_load_xor_8 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_NAND_I8 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_NAND_I8 PSEUDO!",
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[(set GPR:$dst, (atomic_load_nand_8 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_ADD_I16 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_ADD_I16 PSEUDO!",
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[(set GPR:$dst, (atomic_load_add_16 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_SUB_I16 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_SUB_I16 PSEUDO!",
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[(set GPR:$dst, (atomic_load_sub_16 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_AND_I16 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_AND_I16 PSEUDO!",
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[(set GPR:$dst, (atomic_load_and_16 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_OR_I16 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_OR_I16 PSEUDO!",
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[(set GPR:$dst, (atomic_load_or_16 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_XOR_I16 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_XOR_I16 PSEUDO!",
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[(set GPR:$dst, (atomic_load_xor_16 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_NAND_I16 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_NAND_I16 PSEUDO!",
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[(set GPR:$dst, (atomic_load_nand_16 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_ADD_I32 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_ADD_I32 PSEUDO!",
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[(set GPR:$dst, (atomic_load_add_32 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_SUB_I32 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_SUB_I32 PSEUDO!",
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[(set GPR:$dst, (atomic_load_sub_32 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_AND_I32 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_AND_I32 PSEUDO!",
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[(set GPR:$dst, (atomic_load_and_32 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_OR_I32 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_OR_I32 PSEUDO!",
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[(set GPR:$dst, (atomic_load_or_32 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_XOR_I32 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_XOR_I32 PSEUDO!",
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[(set GPR:$dst, (atomic_load_xor_32 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_LOAD_NAND_I32 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$incr), NoItinerary,
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"${:comment} ATOMIC_LOAD_NAND_I32 PSEUDO!",
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[(set GPR:$dst, (atomic_load_nand_32 GPR:$ptr, GPR:$incr))]>;
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def ATOMIC_SWAP_I8 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
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"${:comment} ATOMIC_SWAP_I8 PSEUDO!",
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[(set GPR:$dst, (atomic_swap_8 GPR:$ptr, GPR:$new))]>;
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def ATOMIC_SWAP_I16 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
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"${:comment} ATOMIC_SWAP_I16 PSEUDO!",
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[(set GPR:$dst, (atomic_swap_16 GPR:$ptr, GPR:$new))]>;
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def ATOMIC_SWAP_I32 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$new), NoItinerary,
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"${:comment} ATOMIC_SWAP_I32 PSEUDO!",
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[(set GPR:$dst, (atomic_swap_32 GPR:$ptr, GPR:$new))]>;
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def ATOMIC_CMP_SWAP_I8 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
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"${:comment} ATOMIC_CMP_SWAP_I8 PSEUDO!",
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[(set GPR:$dst, (atomic_cmp_swap_8 GPR:$ptr, GPR:$old, GPR:$new))]>;
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def ATOMIC_CMP_SWAP_I16 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
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"${:comment} ATOMIC_CMP_SWAP_I16 PSEUDO!",
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[(set GPR:$dst, (atomic_cmp_swap_16 GPR:$ptr, GPR:$old, GPR:$new))]>;
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def ATOMIC_CMP_SWAP_I32 : PseudoInst<
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(outs GPR:$dst), (ins GPR:$ptr, GPR:$old, GPR:$new), NoItinerary,
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"${:comment} ATOMIC_CMP_SWAP_I32 PSEUDO!",
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[(set GPR:$dst, (atomic_cmp_swap_32 GPR:$ptr, GPR:$old, GPR:$new))]>;
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}
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}
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let mayLoad = 1 in {
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