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Disengage DEBUG_LOC from non-PPC targets.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@24919 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -622,18 +622,22 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
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case TargetLowering::Promote:
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default: assert(0 && "This action is not supported yet!");
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case TargetLowering::Expand: {
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MachineDebugInfo &DebugInfo = DAG.getMachineFunction().getDebugInfo();
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std::vector<SDOperand> Ops;
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Ops.push_back(Tmp1); // chain
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Ops.push_back(Node->getOperand(1)); // line #
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Ops.push_back(Node->getOperand(2)); // col #
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const std::string &fname =
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cast<StringSDNode>(Node->getOperand(3))->getValue();
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const std::string &dirname =
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cast<StringSDNode>(Node->getOperand(4))->getValue();
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unsigned id = DebugInfo.RecordSource(fname, dirname);
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Ops.push_back(DAG.getConstant(id, MVT::i32)); // source file id
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Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
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if (TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other)) {
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MachineDebugInfo &DebugInfo = DAG.getMachineFunction().getDebugInfo();
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std::vector<SDOperand> Ops;
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Ops.push_back(Tmp1); // chain
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Ops.push_back(Node->getOperand(1)); // line #
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Ops.push_back(Node->getOperand(2)); // col #
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const std::string &fname =
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cast<StringSDNode>(Node->getOperand(3))->getValue();
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const std::string &dirname =
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cast<StringSDNode>(Node->getOperand(4))->getValue();
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unsigned id = DebugInfo.RecordSource(fname, dirname);
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Ops.push_back(DAG.getConstant(id, MVT::i32)); // source file id
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Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
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} else {
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Result = Tmp1; // chain
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}
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Result = LegalizeOp(Result); // Relegalize new nodes.
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break;
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}
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@ -691,7 +691,7 @@ void SimpleSched::VisitAll() {
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} else {
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Ordering.push_back(NI);
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}
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// Iterate through all nodes that have been added
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for (unsigned i = 0; i < Ordering.size(); i++) { // note: size() varies
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// Visit all operands
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@ -102,6 +102,7 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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addLegalFPImmediate(+0.0); //F31
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addLegalFPImmediate(-0.0); //-F31
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@ -74,6 +74,7 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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//IA64 has these, but they are not implemented
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setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
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@ -102,6 +102,7 @@ namespace {
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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computeRegisterProperties();
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@ -147,6 +147,11 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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computeRegisterProperties();
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}
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@ -147,6 +147,11 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
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setOperationAction(ISD::SHL_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRA_PARTS, MVT::i32, Expand);
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setOperationAction(ISD::SRL_PARTS, MVT::i32, Expand);
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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computeRegisterProperties();
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}
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@ -126,6 +126,7 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
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// We don't have line number support yet.
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setOperationAction(ISD::LOCATION, MVT::Other, Expand);
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setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
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if (X86ScalarSSE) {
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// Set up the FP register classes.
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