mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-12-14 11:32:34 +00:00
Clean up Mips16InstrFormats.td and Mips16InstrInfo.td.
Patch by Reed Kotler. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@160403 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Akira Hatanaka
parent
afb24cecff
commit
e882accb7a
@ -14,7 +14,7 @@
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//
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// funct or f Function field
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//
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// immediate 4-,5-,8- or 11-bit immediate, branch displacemen, or
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// immediate 4-,5-,8- or 11-bit immediate, branch displacement, or
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// or imm address displacement
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//
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// op 5-bit major operation code
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@ -65,13 +65,12 @@ def FrmOther16 : Format16<22>; // Instruction w/ a custom format
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// This class does not depend on the instruction size
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//
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class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format16 f>: Instruction
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InstrItinClass itin, Format16 f>: Instruction
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{
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Format16 Form = f;
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let Namespace = "Mips";
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let OutOperandList = outs;
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let InOperandList = ins;
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@ -95,12 +94,12 @@ class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
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//
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class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format16 f>:
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MipsInst16_Base<outs, ins, asmstr, pattern, itin, f>
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MipsInst16_Base<outs, ins, asmstr, pattern, itin, f>
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{
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field bits<16> Inst;
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bits<5> Opcode = 0;
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// Top 6 bits are the 'opcode' field
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// Top 5 bits are the 'opcode' field
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let Inst{15-11} = Opcode;
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}
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@ -109,7 +108,7 @@ class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
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//
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class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format16 f>:
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MipsInst16_Base<outs, ins, asmstr, pattern, itin, f>
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MipsInst16_Base<outs, ins, asmstr, pattern, itin, f>
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{
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field bits<32> Inst;
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@ -117,18 +116,16 @@ class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
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class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin, Format16 f>:
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MipsInst16_32<outs, ins, asmstr, pattern, itin, f>
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MipsInst16_32<outs, ins, asmstr, pattern, itin, f>
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{
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let Inst{31-27} = 0b11110;
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}
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// Mips Pseudo Instructions Format
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class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
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MipsInst16<outs, ins, asmstr, pattern, IIPseudo, Pseudo16> {
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MipsInst16<outs, ins, asmstr, pattern, IIPseudo, Pseudo16> {
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let isCodeGenOnly = 1;
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let isPseudo = 1;
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}
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@ -139,8 +136,8 @@ class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
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//===----------------------------------------------------------------------===//
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class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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InstrItinClass itin>: MipsInst16<outs, ins, asmstr, pattern,
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itin, FrmI16>
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InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmI16>
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{
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bits<11> imm11;
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@ -155,7 +152,7 @@ class FI16<bits<5> op, dag outs, dag ins, string asmstr, list<dag> pattern,
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class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRI16>
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRI16>
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{
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bits<3> rx;
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bits<8> imm8;
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@ -172,7 +169,7 @@ class FRI16<bits<5> op, dag outs, dag ins, string asmstr,
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class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
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{
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bits<3> rx;
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bits<3> ry;
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@ -186,19 +183,60 @@ class FRR16<bits<5> _funct, dag outs, dag ins, string asmstr,
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let Inst{4-0} = funct;
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}
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//
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// For conversion functions.
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//
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class FRR_SF16<bits<5> _funct, bits<3> _subfunct, dag outs, dag ins,
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string asmstr, list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
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{
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bits<3> rx;
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bits<3> subfunct;
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bits<5> funct;
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let Opcode = 0b11101; // RR
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let funct = _funct;
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let subfunct = _subfunct;
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let Inst{10-8} = rx;
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let Inst{7-5} = subfunct;
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let Inst{4-0} = funct;
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}
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//
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// just used for breakpoint (hardware and software) instructions.
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//
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class FC16<bits<5> _funct, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
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{
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bits<6> _code; // code is a keyword in tablegen
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bits<5> funct;
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let Opcode = 0b11101; // RR
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let funct = _funct;
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let Inst{10-5} = _code;
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let Inst{4-0} = funct;
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}
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//
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// J(AL)R(C) subformat
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//
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class FRR16_JALRC<dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
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class FRR16_JALRC<bits<1> _nd, bits<1> _l, bits<1> r_a,
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dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRR16>
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{
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bits<3> rx;
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bits<1> nd;
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bits<1> l;
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bits<1> ra;
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let nd = _nd;
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let l = _l;
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let ra = r_a;
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let Opcode = 0b11101;
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let Inst{10-8} = rx;
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@ -214,7 +252,7 @@ class FRR16_JALRC<dag outs, dag ins, string asmstr,
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class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRI16>
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRI16>
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{
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bits<3> rx;
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bits<3> ry;
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@ -232,16 +270,16 @@ class FRRI16<bits<5> op, dag outs, dag ins, string asmstr,
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// Format RRR instruction class in Mips : <|opcode|rx|ry|rz|f|>
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//===----------------------------------------------------------------------===//
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class FRRR16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
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class FRRR16<bits<2> _f, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRR16>
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRR16>
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{
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bits<3> rx;
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bits<3> ry;
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bits<3> rz;
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bits<2> f;
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let Opcode = op;
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let Opcode = 0b11100;
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let f = _f;
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let Inst{10-8} = rx;
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@ -254,16 +292,16 @@ class FRRR16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
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// Format RRI-A instruction class in Mips : <|opcode|rx|ry|f|imm4|>
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//===----------------------------------------------------------------------===//
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class FRRI_A16<bits<5> op, bits<1> _f, dag outs, dag ins, string asmstr,
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class FRRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRI_A16>
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmRRI_A16>
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{
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bits<3> rx;
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bits<3> ry;
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bits<1> f;
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bits<4> imm4;
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let Opcode = op;
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let Opcode = 0b01000;
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let f = _f;
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let Inst{10-8} = rx;
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@ -276,16 +314,16 @@ class FRRI_A16<bits<5> op, bits<1> _f, dag outs, dag ins, string asmstr,
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// Format Shift instruction class in Mips : <|opcode|rx|ry|sa|f|>
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//===----------------------------------------------------------------------===//
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class FSHIFT16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
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class FSHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmSHIFT16>
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmSHIFT16>
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{
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bits<3> rx;
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bits<3> ry;
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bits<3> sa;
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bits<2> f;
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let Opcode = op;
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let Opcode = 0b00110;
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let f = _f;
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let Inst{10-8} = rx;
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@ -298,14 +336,14 @@ class FSHIFT16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
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// Format i8 instruction class in Mips : <|opcode|funct|imm8>
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//===----------------------------------------------------------------------===//
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class FI816<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
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class FI816<bits<3> _func, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_TYPE16>
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_TYPE16>
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{
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bits<3> func;
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bits<8> imm8;
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let Opcode = op;
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let Opcode = 0b01100;
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let func = _func;
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let Inst{10-8} = func;
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@ -316,19 +354,17 @@ class FI816<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
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// Format i8_MOVR32 instruction class in Mips : <|opcode|func|ry|r32>
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//===----------------------------------------------------------------------===//
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class FI8_MOVR3216<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
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class FI8_MOVR3216<dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_MOVR3216>
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_MOVR3216>
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{
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bits<3> func;
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bits<4> ry;
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bits<4> r32;
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let Opcode = op;
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let func = _func;
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let Opcode = 0b01100;
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let Inst{10-8} = func;
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let Inst{10-8} = 0b111;
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let Inst{7-4} = ry;
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let Inst{3-0} = r32;
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@ -337,12 +373,12 @@ class FI8_MOVR3216<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
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//===----------------------------------------------------------------------===//
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// Format i8_MOV32R instruction class in Mips : <|opcode|func|ry|r32>
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// Format i8_MOV32R instruction class in Mips : <|opcode|func|r32|rz>
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//===----------------------------------------------------------------------===//
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class FI8_MOV32R16<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
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class FI8_MOV32R16<dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_MOV32R16>
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_MOV32R16>
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{
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bits<3> func;
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@ -350,10 +386,9 @@ class FI8_MOV32R16<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
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bits<3> rz;
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let Opcode = op;
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let func = _func;
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let Opcode = 0b01100;
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let Inst{10-8} = func;
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let Inst{10-8} = 0b101;
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let Inst{7-5} = r32{2-0};
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let Inst{4-3} = r32{4-3};
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let Inst{2-0} = rz;
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@ -365,21 +400,20 @@ class FI8_MOV32R16<bits<5> op, bits<3> _func, dag outs, dag ins, string asmstr,
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// <|opcode|svrs|s|ra|s0|s1|framesize>
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//===----------------------------------------------------------------------===//
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class FI8_SVRS16<bits<5> op, bits<3> _SVRS, dag outs, dag ins, string asmstr,
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class FI8_SVRS16<bits<1> _s, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_SVRS16>
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MipsInst16<outs, ins, asmstr, pattern, itin, FrmI8_SVRS16>
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{
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bits<3> SVRS;
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bits<1> s;
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bits<1> ra;
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bits<1> s0;
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bits<1> s1;
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bits<4> framesize;
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bits<1> ra = 0;
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bits<1> s0 = 0;
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bits<1> s1 = 0;
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bits<4> framesize = 0;
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let Opcode = op;
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let SVRS = _SVRS;
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let s =_s;
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let Opcode = 0b01100;
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let Inst{10-8} = SVRS;
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let Inst{10-8} = 0b100;
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let Inst{7} = s;
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let Inst{6} = ra;
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let Inst{5} = s0;
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@ -393,9 +427,9 @@ class FI8_SVRS16<bits<5> op, bits<3> _SVRS, dag outs, dag ins, string asmstr,
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// <|opcode|svrs|s|ra|s0|s1|framesize>
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//===----------------------------------------------------------------------===//
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class FJAL16<bits<5> op, bits<1> _X, dag outs, dag ins, string asmstr,
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class FJAL16<bits<1> _X, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_32<outs, ins, asmstr, pattern, itin, FrmJAL16>
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MipsInst16_32<outs, ins, asmstr, pattern, itin, FrmJAL16>
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{
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bits<1> X;
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bits<26> imm26;
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@ -411,7 +445,6 @@ class FJAL16<bits<5> op, bits<1> _X, dag outs, dag ins, string asmstr,
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}
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//===----------------------------------------------------------------------===//
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// Format EXT-I instruction class in Mips16 :
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// <|EXTEND|imm10:5|imm15:11|op|0|0|0|0|0|0|imm4:0>
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@ -419,7 +452,7 @@ class FJAL16<bits<5> op, bits<1> _X, dag outs, dag ins, string asmstr,
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class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_I16>
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_I16>
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{
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bits<16> imm16;
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bits<5> eop;
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@ -434,25 +467,19 @@ class FEXT_I16<bits<5> _eop, dag outs, dag ins, string asmstr,
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}
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//===----------------------------------------------------------------------===//
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// Format ASMACRO instruction class in Mips16 :
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// <EXTEND|select|p4|p3|RRR|p2|p1|p0>
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//===----------------------------------------------------------------------===//
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class FASMACRO16<bits<5> op, dag outs, dag ins, string asmstr,
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class FASMACRO16<dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
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FrmASMACRO16>
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmASMACRO16>
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{
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bits<3> select;
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bits<3> p4;
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bits<5> p3;
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bits<5> RRR;
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bits<5> RRR = 0b11100;
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bits<3> p2;
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bits<3> p1;
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bits<5> p0;
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@ -476,8 +503,7 @@ class FASMACRO16<bits<5> op, dag outs, dag ins, string asmstr,
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class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
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list<dag> pattern, InstrItinClass itin>:
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
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FrmEXT_RI16>
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MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_RI16>
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{
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bits<16> imm16;
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bits<5> op;
|
||||
@ -501,8 +527,7 @@ class FEXT_RI16<bits<5> _op, dag outs, dag ins, string asmstr,
|
||||
|
||||
class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,
|
||||
list<dag> pattern, InstrItinClass itin>:
|
||||
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
|
||||
FrmEXT_RRI16>
|
||||
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_RRI16>
|
||||
{
|
||||
bits<16> imm16;
|
||||
bits<3> rx;
|
||||
@ -525,8 +550,7 @@ class FEXT_RRI16<bits<5> _op, dag outs, dag ins, string asmstr,
|
||||
|
||||
class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
|
||||
list<dag> pattern, InstrItinClass itin>:
|
||||
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
|
||||
FrmEXT_RRI_A16>
|
||||
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_RRI_A16>
|
||||
{
|
||||
bits<15> imm15;
|
||||
bits<3> rx;
|
||||
@ -550,10 +574,9 @@ class FEXT_RRI_A16<bits<1> _f, dag outs, dag ins, string asmstr,
|
||||
// <|EXTEND|sa 4:0|s5|0|SHIFT|rx|ry|0|f>
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class FEXT_SHIFT16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
|
||||
class FEXT_SHIFT16<bits<2> _f, dag outs, dag ins, string asmstr,
|
||||
list<dag> pattern, InstrItinClass itin>:
|
||||
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
|
||||
FrmEXT_SHIFT16>
|
||||
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_SHIFT16>
|
||||
{
|
||||
bits<6> sa6;
|
||||
bits<3> rx;
|
||||
@ -580,14 +603,14 @@ class FEXT_SHIFT16<bits<5> op, bits<2> _f, dag outs, dag ins, string asmstr,
|
||||
|
||||
class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
|
||||
list<dag> pattern, InstrItinClass itin>:
|
||||
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
|
||||
FrmEXT_I816>
|
||||
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmEXT_I816>
|
||||
{
|
||||
bits<16> imm16;
|
||||
bits<5> I8;
|
||||
bits<3> funct;
|
||||
|
||||
let funct = _funct;
|
||||
let I8 = 0b0110;
|
||||
|
||||
let Inst{26-21} = imm16{10-5};
|
||||
let Inst{20-16} = imm16{15-11};
|
||||
@ -603,21 +626,21 @@ class FEXT_I816<bits<3> _funct, dag outs, dag ins, string asmstr,
|
||||
// <|EXTEND|xsregs|framesize7:4|aregs|I8|SVRS|s|ra|s0|s1|framesize3:0>
|
||||
//===----------------------------------------------------------------------===//
|
||||
|
||||
class FEXT_I8_SVRS16<dag outs, dag ins, string asmstr,
|
||||
class FEXT_I8_SVRS16<bits<1> s_, dag outs, dag ins, string asmstr,
|
||||
list<dag> pattern, InstrItinClass itin>:
|
||||
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin,
|
||||
FrmI8_SVRS16>
|
||||
MipsInst16_EXTEND<outs, ins, asmstr, pattern, itin, FrmI8_SVRS16>
|
||||
{
|
||||
bits<3> xsregs;
|
||||
bits<8> framesize;
|
||||
bits<3> aregs;
|
||||
bits<5> I8;
|
||||
bits<3> SVRS;
|
||||
bits<3> xsregs =0;
|
||||
bits<8> framesize =0;
|
||||
bits<3> aregs =0;
|
||||
bits<5> I8 = 0b01100;
|
||||
bits<3> SVRS = 0b100;
|
||||
bits<1> s;
|
||||
bits<1> ra;
|
||||
bits<1> s0;
|
||||
bits<1> s1;
|
||||
bits<1> ra = 0;
|
||||
bits<1> s0 = 0;
|
||||
bits<1> s1 = 0;
|
||||
|
||||
let s= s_;
|
||||
|
||||
let Inst{26-24} = xsregs;
|
||||
let Inst{23-20} = framesize{7-4};
|
||||
|
||||
@ -26,9 +26,9 @@ def LI16E : FEXT_RI16<0b01101, (outs CPU16Regs:$rx),
|
||||
[(set CPU16Regs:$rx, immZExt16:$amt )],IILoad>;
|
||||
|
||||
let isReturn=1, isTerminator=1, hasDelaySlot=1, isCodeGenOnly=1,
|
||||
isBarrier=1, hasCtrlDep=1, rx=0, nd=0, l=0, ra=0 in
|
||||
def RET16 : FRR16_JALRC<(outs), (ins CPURAReg:$target), "jr\t$target", [],
|
||||
IIBranch>;
|
||||
isBarrier=1, hasCtrlDep=1, rx=0 in
|
||||
def RET16 : FRR16_JALRC
|
||||
<0,0,0, (outs), (ins CPURAReg:$target), "jr\t$target", [], IIBranch>;
|
||||
|
||||
// As stack alignment is always done with addiu, we need a 16-bit immediate
|
||||
let Defs = [SP], Uses = [SP] in {
|
||||
@ -42,10 +42,11 @@ def ADJCALLSTACKUP16 : MipsPseudo16<(outs), (ins uimm16:$amt1, uimm16:$amt2),
|
||||
|
||||
|
||||
// Jump and Link (Call)
|
||||
let isCall=1, hasDelaySlot=1, nd=0, l=0, ra=0 in
|
||||
let isCall=1, hasDelaySlot=1 in
|
||||
def JumpLinkReg16:
|
||||
FRR16_JALRC<(outs), (ins CPU16Regs:$rs),
|
||||
"jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
|
||||
FRR16_JALRC<0, 0, 0, (outs), (ins CPU16Regs:$rs),
|
||||
"jalr \t$rs", [(MipsJmpLink CPU16Regs:$rs)], IIBranch>;
|
||||
|
||||
|
||||
// Small immediates
|
||||
def : Mips16Pat<(i32 immZExt16:$in), (LI16E immZExt16:$in)>;
|
||||
|
||||
Loading…
Reference in New Issue
Block a user