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Improve sub-register def handling in ProcessImplicitDefs.
This boils down to using MachineOperand::readsReg() more. This fixes PR11829 where a use ended up after the first def when lowering REG_SEQUENCE instructions involving IMPLICIT_DEFs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@148996 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -50,10 +50,10 @@ ProcessImplicitDefs::CanTurnIntoImplicitDef(MachineInstr *MI,
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SmallSet<unsigned, 8> &ImpDefRegs) {
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switch(OpIdx) {
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case 1:
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return MI->isCopy() && (MI->getOperand(0).getSubReg() == 0 ||
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return MI->isCopy() && (!MI->getOperand(0).readsReg() ||
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ImpDefRegs.count(MI->getOperand(0).getReg()));
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case 2:
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return MI->isSubregToReg() && (MI->getOperand(0).getSubReg() == 0 ||
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return MI->isSubregToReg() && (!MI->getOperand(0).readsReg() ||
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ImpDefRegs.count(MI->getOperand(0).getReg()));
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default: return false;
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}
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@ -66,7 +66,7 @@ static bool isUndefCopy(MachineInstr *MI, unsigned Reg,
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MachineOperand &MO1 = MI->getOperand(1);
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if (MO1.getReg() != Reg)
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return false;
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if (!MO0.getSubReg() || ImpDefRegs.count(MO0.getReg()))
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if (!MO0.readsReg() || ImpDefRegs.count(MO0.getReg()))
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return true;
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return false;
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}
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@ -105,7 +105,9 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
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MachineInstr *MI = &*I;
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++I;
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if (MI->isImplicitDef()) {
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if (MI->getOperand(0).getSubReg())
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ImpDefMIs.push_back(MI);
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// Is this a sub-register read-modify-write?
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if (MI->getOperand(0).readsReg())
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continue;
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unsigned Reg = MI->getOperand(0).getReg();
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ImpDefRegs.insert(Reg);
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@ -113,12 +115,11 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
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for (const unsigned *SS = TRI->getSubRegisters(Reg); *SS; ++SS)
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ImpDefRegs.insert(*SS);
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}
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ImpDefMIs.push_back(MI);
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continue;
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}
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// Eliminate %reg1032:sub<def> = COPY undef.
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if (MI->isCopy() && MI->getOperand(0).getSubReg()) {
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if (MI->isCopy() && MI->getOperand(0).readsReg()) {
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MachineOperand &MO = MI->getOperand(1);
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if (MO.isUndef() || ImpDefRegs.count(MO.getReg())) {
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if (MO.isKill()) {
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@ -140,7 +141,7 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
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bool ChangedToImpDef = false;
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for (unsigned i = 0, e = MI->getNumOperands(); i != e; ++i) {
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MachineOperand& MO = MI->getOperand(i);
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if (!MO.isReg() || (MO.isDef() && !MO.getSubReg()) || MO.isUndef())
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if (!MO.isReg() || !MO.readsReg())
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continue;
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unsigned Reg = MO.getReg();
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if (!Reg)
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@ -172,10 +173,10 @@ bool ProcessImplicitDefs::runOnMachineFunction(MachineFunction &fn) {
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continue;
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}
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if (MO.isKill() || MI->isRegTiedToDefOperand(i)) {
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// Make sure other uses of
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// Make sure other reads of Reg are also marked <undef>.
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for (unsigned j = i+1; j != e; ++j) {
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MachineOperand &MOJ = MI->getOperand(j);
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if (MOJ.isReg() && MOJ.isUse() && MOJ.getReg() == Reg)
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if (MOJ.isReg() && MOJ.getReg() == Reg && MOJ.readsReg())
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MOJ.setIsUndef();
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}
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ImpDefRegs.erase(Reg);
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@ -1,5 +1,6 @@
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; RUN: llc < %s -mcpu=cortex-a8 -verify-machineinstrs -verify-coalescing
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; PR11841
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; PR11829
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:64:128-a0:0:64-n32-S64"
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target triple = "armv7-none-linux-eabi"
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@ -37,7 +38,30 @@ bb:
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ret void
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}
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define arm_aapcs_vfpcc void @foo2() nounwind uwtable {
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entry:
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br i1 undef, label %for.end, label %cond.end295
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cond.end295: ; preds = %entry
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%shuffle.i39.i.i1035 = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer
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%shuffle.i38.i.i1036 = shufflevector <2 x i64> zeroinitializer, <2 x i64> undef, <1 x i32> zeroinitializer
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%shuffle.i37.i.i1037 = shufflevector <1 x i64> %shuffle.i39.i.i1035, <1 x i64> %shuffle.i38.i.i1036, <2 x i32> <i32 0, i32 1>
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%0 = bitcast <2 x i64> %shuffle.i37.i.i1037 to <4 x float>
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%1 = bitcast <4 x float> undef to <2 x i64>
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%shuffle.i36.i.i = shufflevector <2 x i64> %1, <2 x i64> undef, <1 x i32> zeroinitializer
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%shuffle.i35.i.i = shufflevector <2 x i64> undef, <2 x i64> undef, <1 x i32> zeroinitializer
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%shuffle.i34.i.i = shufflevector <1 x i64> %shuffle.i36.i.i, <1 x i64> %shuffle.i35.i.i, <2 x i32> <i32 0, i32 1>
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%2 = bitcast <2 x i64> %shuffle.i34.i.i to <4 x float>
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tail call void @llvm.arm.neon.vst1.v4f32(i8* undef, <4 x float> %0, i32 4) nounwind
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tail call void @llvm.arm.neon.vst1.v4f32(i8* undef, <4 x float> %2, i32 4) nounwind
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unreachable
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for.end: ; preds = %entry
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ret void
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}
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declare arm_aapcs_vfpcc void @bar(i8*, float, float, float)
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declare void @llvm.arm.neon.vst1.v4f32(i8*, <4 x float>, i32) nounwind
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!0 = metadata !{metadata !"omnipotent char", metadata !1}
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!1 = metadata !{metadata !"Simple C/C++ TBAA", null}
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