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LHS = X86ISD::CMOVcc LHS, RHS means LHS = RHS if cc. So the operands must be

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flipped around.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25290 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Evan Cheng 2006-01-13 19:51:46 +00:00
parent 874357fa75
commit e90da97f3e
1 changed files with 4 additions and 2 deletions
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6
lib/Target/X86/X86ISelLowering.cpp
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@ -1606,7 +1606,7 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
addTest = true;
if (addTest) {
CC = DAG.getConstant(X86ISD::COND_E, MVT::i8);
CC = DAG.getConstant(X86ISD::COND_NE, MVT::i8);
Cond = DAG.getNode(X86ISD::TEST, MVT::Flag, Op0, Op0);
}
@ -1614,8 +1614,10 @@ SDOperand X86TargetLowering::LowerOperation(SDOperand Op, SelectionDAG &DAG) {
Tys.push_back(Op.getValueType());
Tys.push_back(MVT::Flag);
std::vector<SDOperand> Ops;
Ops.push_back(Op.getOperand(1));
// X86ISD::CMOV means set the result (which is operand 1) to the RHS if
// condition is true.
Ops.push_back(Op.getOperand(2));
Ops.push_back(Op.getOperand(1));
Ops.push_back(CC);
Ops.push_back(Cond);
return DAG.getNode(X86ISD::CMOV, Tys, Ops);