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ARM: fix VEXT encoding corner case

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The disassembly of VEXT instructions was too lax in the bits checked. This
fixes the case where the instruction affects Q-registers but a misaligned lane
was specified (should be UNDEFINED).

Patch by Amaury de la Vieuville

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183003 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Tim Northover
2013-05-31 13:47:25 +00:00
parent b6606e46ab
commit e93c701cac
2 changed files with 11 additions and 5 deletions
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5
test/MC/Disassembler/ARM/invalid-VEXTd-arm.txt Normal file
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@@ -0,0 +1,5 @@
# RUN: llvm-mc --disassemble %s -triple=armv7 2>&1 | grep "invalid instruction encoding"
# invalid imm4 value (0b1xxx)
# A8.8.316: if Q == '0' && imm4<3> == '1' then UNDEFINED;
0x8f 0xf9 0xf7 0xf2