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LLVM backend for 6502
e93c701cac
The disassembly of VEXT instructions was too lax in the bits checked. This fixes the case where the instruction affects Q-registers but a misaligned lane was specified (should be UNDEFINED). Patch by Amaury de la Vieuville git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183003 91177308-0d34-0410-b5e6-96231b3b80d8 |
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| autoconf | ||
| bindings | ||
| cmake | ||
| docs | ||
| examples | ||
| include | ||
| lib | ||
| projects | ||
| runtime | ||
| test | ||
| tools | ||
| unittests | ||
| utils | ||
| .arcconfig | ||
| .gitignore | ||
| CMakeLists.txt | ||
| CODE_OWNERS.TXT | ||
| configure | ||
| CREDITS.TXT | ||
| LICENSE.TXT | ||
| llvm.spec.in | ||
| LLVMBuild.txt | ||
| Makefile | ||
| Makefile.common | ||
| Makefile.config.in | ||
| Makefile.rules | ||
| README.txt | ||
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