6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-07-05 13:29:22 +00:00
Code Issues Projects Releases Wiki Activity

Keep track of incoming argument's location while emitting LiveIns.

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@124611 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Devang Patel 2011-01-31 21:38:14 +00:00
parent 97f6d5b241
commit e9a7ea6865
13 changed files with 144 additions and 32 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
include/llvm/CodeGen/MachineFunction.h
View File

@ -281,7 +281,7 @@ public:
/// addLiveIn - Add the specified physical register as a live-in value and
/// create a corresponding virtual register for it.
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC);
unsigned addLiveIn(unsigned PReg, const TargetRegisterClass *RC, DebugLoc DL);
//===--------------------------------------------------------------------===//
// BasicBlock accessor functions.

14
include/llvm/CodeGen/MachineRegisterInfo.h
View File

@ -17,6 +17,8 @@
#include "llvm/Target/TargetRegisterInfo.h"
#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/IndexedMap.h"
#include "llvm/ADT/DenseMap.h"
#include "llvm/Support/DebugLoc.h"
#include <vector>
namespace llvm {
@ -64,7 +66,10 @@ class MachineRegisterInfo {
/// stored in the second element.
std::vector<std::pair<unsigned, unsigned> > LiveIns;
std::vector<unsigned> LiveOuts;
/// LiveInLocs - Keep track of location livein registers.
DenseMap<unsigned, DebugLoc> LiveInLocs;
MachineRegisterInfo(const MachineRegisterInfo&); // DO NOT IMPLEMENT
void operator=(const MachineRegisterInfo&); // DO NOT IMPLEMENT
public:
@ -271,7 +276,12 @@ public:
LiveIns.push_back(std::make_pair(Reg, vreg));
}
void addLiveOut(unsigned Reg) { LiveOuts.push_back(Reg); }
/// addLiveInLoc - Keep track of location info for live in reg.
void addLiveInLoc(unsigned VReg, DebugLoc DL) {
LiveInLocs[VReg] = DL;
}
// Iteration support for live in/out sets. These sets are kept in sorted
// order by their register number.
typedef std::vector<std::pair<unsigned,unsigned> >::const_iterator

4
lib/CodeGen/MachineFunction.cpp
View File

@ -396,7 +396,8 @@ void MachineFunction::viewCFGOnly() const
/// addLiveIn - Add the specified physical register as a live-in value and
/// create a corresponding virtual register for it.
unsigned MachineFunction::addLiveIn(unsigned PReg,
const TargetRegisterClass *RC) {
const TargetRegisterClass *RC,
DebugLoc DL) {
MachineRegisterInfo &MRI = getRegInfo();
unsigned VReg = MRI.getLiveInVirtReg(PReg);
if (VReg) {
@ -405,6 +406,7 @@ unsigned MachineFunction::addLiveIn(unsigned PReg,
}
VReg = MRI.createVirtualRegister(RC);
MRI.addLiveIn(PReg, VReg);
MRI.addLiveInLoc(VReg, DL);
return VReg;
}

9
lib/CodeGen/MachineRegisterInfo.cpp
View File

@ -210,8 +210,15 @@ MachineRegisterInfo::EmitLiveInCopies(MachineBasicBlock *EntryMBB,
LiveIns.erase(LiveIns.begin() + i);
--i; --e;
} else {
DebugLoc DL;
// If there is a location for this live in then use it.
DenseMap<unsigned, DebugLoc>::iterator DLI =
LiveInLocs.find(LiveIns[i].second);
if (DLI != LiveInLocs.end())
DL = DLI->second;
// Emit a copy.
BuildMI(*EntryMBB, EntryMBB->begin(), DebugLoc(),
BuildMI(*EntryMBB, EntryMBB->begin(), DL,
TII.get(TargetOpcode::COPY), LiveIns[i].second)
.addReg(LiveIns[i].first);

2
lib/CodeGen/SelectionDAG/SelectionDAGBuilder.h
View File

@ -348,7 +348,7 @@ public:
SDValue getControlRoot();
DebugLoc getCurDebugLoc() const { return CurDebugLoc; }
void setCurDebugLoc(DebugLoc dl){ CurDebugLoc = dl; }
unsigned getSDNodeOrder() const { return SDNodeOrder; }
void CopyValueToVirtualRegister(const Value *V, unsigned Reg);

11
lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
View File

@ -851,8 +851,17 @@ void SelectionDAGISel::SelectAllBasicBlocks(const Function &Fn) {
PrepareEHLandingPad();
// Lower any arguments needed in this block if this is the entry block.
if (LLVMBB == &Fn.getEntryBlock())
if (LLVMBB == &Fn.getEntryBlock()) {
for (BasicBlock::const_iterator DBI = LLVMBB->begin(), DBE = LLVMBB->end();
DBI != DBE; ++DBI) {
if (const DbgInfoIntrinsic *DI = dyn_cast<DbgInfoIntrinsic>(DBI)) {
const DebugLoc DL = DI->getDebugLoc();
SDB->setCurDebugLoc(DL);
break;
}
}
LowerArguments(LLVMBB);
}
// Before doing SelectionDAG ISel, see if FastISel has been requested.
if (FastIS) {

10
lib/Target/ARM/ARMISelLowering.cpp
View File

@ -2212,7 +2212,7 @@ ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
RC = ARM::GPRRegisterClass;
// Transform the arguments stored in physical registers into virtual ones.
unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC, dl);
SDValue ArgValue = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
SDValue ArgValue2;
@ -2226,7 +2226,7 @@ ARMTargetLowering::GetF64FormalArgument(CCValAssign &VA, CCValAssign &NextVA,
MachinePointerInfo::getFixedStack(FI),
false, false, 0);
} else {
Reg = MF.addLiveIn(NextVA.getLocReg(), RC);
Reg = MF.addLiveIn(NextVA.getLocReg(), RC, dl);
ArgValue2 = DAG.getCopyFromReg(Root, dl, Reg, MVT::i32);
}
@ -2307,7 +2307,7 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
llvm_unreachable("RegVT not supported by FORMAL_ARGUMENTS Lowering");
// Transform the arguments in physical registers into virtual ones.
unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC, dl);
ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
}
@ -2384,7 +2384,7 @@ ARMTargetLowering::LowerFormalArguments(SDValue Chain,
else
RC = ARM::GPRRegisterClass;
unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC);
unsigned VReg = MF.addLiveIn(GPRArgRegs[NumGPRs], RC, dl);
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
SDValue Store =
DAG.getStore(Val.getValue(1), dl, Val, FIN,
@ -2839,7 +2839,7 @@ SDValue ARMTargetLowering::LowerRETURNADDR(SDValue Op, SelectionDAG &DAG) const{
}
// Return LR, which contains the return address. Mark it an implicit live-in.
unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32));
unsigned Reg = MF.addLiveIn(ARM::LR, getRegClassFor(MVT::i32), dl);
return DAG.getCopyFromReg(DAG.getEntryNode(), dl, Reg, VT);
}

2
lib/Target/CellSPU/SPUISelLowering.cpp
View File

@ -1219,7 +1219,7 @@ SPUTargetLowering::LowerFormalArguments(SDValue Chain,
FuncInfo->setVarArgsFrameIndex(
MFI->CreateFixedObject(StackSlotSize, ArgOffset, true));
SDValue FIN = DAG.getFrameIndex(FuncInfo->getVarArgsFrameIndex(), PtrVT);
unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::R32CRegClass);
unsigned VReg = MF.addLiveIn(ArgRegs[ArgRegIdx], &SPU::R32CRegClass, dl);
SDValue ArgVal = DAG.getRegister(VReg, MVT::v16i8);
SDValue Store = DAG.getStore(Chain, dl, ArgVal, FIN, MachinePointerInfo(),
false, false, 0);

4
lib/Target/MBlaze/MBlazeISelLowering.cpp
View File

@ -907,7 +907,7 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
// Transform the arguments stored on
// physical registers into virtual ones
unsigned Reg = MF.addLiveIn(ArgRegEnd, RC);
unsigned Reg = MF.addLiveIn(ArgRegEnd, RC, dl);
SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
// If this is an 8 or 16-bit value, it has been passed promoted
@ -973,7 +973,7 @@ LowerFormalArguments(SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
for (; Start <= End; ++Start, ++StackLoc) {
unsigned Reg = MBlazeRegisterInfo::getRegisterFromNumbering(Start);
unsigned LiveReg = MF.addLiveIn(Reg, RC);
unsigned LiveReg = MF.addLiveIn(Reg, RC, dl);
SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, LiveReg, MVT::i32);
int FI = MFI->CreateFixedObject(4, 0, true);

24
lib/Target/PowerPC/PPCISelLowering.cpp
View File

@ -1597,7 +1597,7 @@ PPCTargetLowering::LowerFormalArguments_SVR4(
}
// Transform the arguments stored in physical registers into virtual ones.
unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC, dl);
SDValue ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, ValVT);
InVals.push_back(ArgValue);
@ -1689,7 +1689,7 @@ PPCTargetLowering::LowerFormalArguments_SVR4(
// Get an existing live-in vreg, or add a new one.
unsigned VReg = MF.getRegInfo().getLiveInVirtReg(GPArgRegs[GPRIndex]);
if (!VReg)
VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass);
VReg = MF.addLiveIn(GPArgRegs[GPRIndex], &PPC::GPRCRegClass, dl);
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
@ -1708,7 +1708,7 @@ PPCTargetLowering::LowerFormalArguments_SVR4(
// Get an existing live-in vreg, or add a new one.
unsigned VReg = MF.getRegInfo().getLiveInVirtReg(FPArgRegs[FPRIndex]);
if (!VReg)
VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass);
VReg = MF.addLiveIn(FPArgRegs[FPRIndex], &PPC::F8RCRegClass, dl);
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::f64);
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,
@ -1872,7 +1872,7 @@ PPCTargetLowering::LowerFormalArguments_Darwin(
InVals.push_back(FIN);
if (ObjSize==1 || ObjSize==2) {
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass, dl);
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
SDValue Store = DAG.getTruncStore(Val.getValue(1), dl, Val, FIN,
MachinePointerInfo(),
@ -1891,7 +1891,7 @@ PPCTargetLowering::LowerFormalArguments_Darwin(
// to memory. ArgVal will be address of the beginning of
// the object.
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass, dl);
int FI = MFI->CreateFixedObject(PtrByteSize, ArgOffset, true);
SDValue FIN = DAG.getFrameIndex(FI, PtrVT);
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
@ -1914,7 +1914,7 @@ PPCTargetLowering::LowerFormalArguments_Darwin(
case MVT::i32:
if (!isPPC64) {
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass, dl);
ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i32);
++GPR_idx;
} else {
@ -1928,7 +1928,7 @@ PPCTargetLowering::LowerFormalArguments_Darwin(
// FALLTHROUGH
case MVT::i64: // PPC64
if (GPR_idx != Num_GPR_Regs) {
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
unsigned VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass, dl);
ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
if (ObjectVT == MVT::i32) {
@ -1966,9 +1966,9 @@ PPCTargetLowering::LowerFormalArguments_Darwin(
unsigned VReg;
if (ObjectVT == MVT::f32)
VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass);
VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F4RCRegClass, dl);
else
VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass);
VReg = MF.addLiveIn(FPR[FPR_idx], &PPC::F8RCRegClass, dl);
ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
++FPR_idx;
@ -1986,7 +1986,7 @@ PPCTargetLowering::LowerFormalArguments_Darwin(
// Note that vector arguments in registers don't reserve stack space,
// except in varargs functions.
if (VR_idx != Num_VR_Regs) {
unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass);
unsigned VReg = MF.addLiveIn(VR[VR_idx], &PPC::VRRCRegClass, dl);
ArgVal = DAG.getCopyFromReg(Chain, dl, VReg, ObjectVT);
if (isVarArg) {
while ((ArgOffset % 16) != 0) {
@ -2064,9 +2064,9 @@ PPCTargetLowering::LowerFormalArguments_Darwin(
unsigned VReg;
if (isPPC64)
VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass);
VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::G8RCRegClass, dl);
else
VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass);
VReg = MF.addLiveIn(GPR[GPR_idx], &PPC::GPRCRegClass, dl);
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, PtrVT);
SDValue Store = DAG.getStore(Val.getValue(1), dl, Val, FIN,

2
lib/Target/Sparc/SparcISelLowering.cpp
View File

@ -194,7 +194,7 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain,
false, false, 0);
} else {
unsigned loReg = MF.addLiveIn(NextVA.getLocReg(),
&SP::IntRegsRegClass);
&SP::IntRegsRegClass, dl);
LoVal = DAG.getCopyFromReg(Chain, dl, loReg, MVT::i32);
}
SDValue WholeValue =

8
lib/Target/X86/X86ISelLowering.cpp
View File

@ -1576,7 +1576,7 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
else
llvm_unreachable("Unknown argument type!");
unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC);
unsigned Reg = MF.addLiveIn(VA.getLocReg(), RC, dl);
ArgValue = DAG.getCopyFromReg(Chain, dl, Reg, RegVT);
// If this is an 8 or 16-bit value, it is really passed promoted to 32
@ -1708,7 +1708,7 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
SDValue FIN = DAG.getNode(ISD::ADD, dl, getPointerTy(), RSFIN,
DAG.getIntPtrConstant(Offset));
unsigned VReg = MF.addLiveIn(GPR64ArgRegs[NumIntRegs],
X86::GR64RegisterClass);
X86::GR64RegisterClass, dl);
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::i64);
SDValue Store =
DAG.getStore(Val.getValue(1), dl, Val, FIN,
@ -1724,7 +1724,7 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
SmallVector<SDValue, 11> SaveXMMOps;
SaveXMMOps.push_back(Chain);
unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass);
unsigned AL = MF.addLiveIn(X86::AL, X86::GR8RegisterClass, dl);
SDValue ALVal = DAG.getCopyFromReg(DAG.getEntryNode(), dl, AL, MVT::i8);
SaveXMMOps.push_back(ALVal);
@ -1735,7 +1735,7 @@ X86TargetLowering::LowerFormalArguments(SDValue Chain,
for (; NumXMMRegs != TotalNumXMMRegs; ++NumXMMRegs) {
unsigned VReg = MF.addLiveIn(XMMArgRegs64Bit[NumXMMRegs],
X86::VR128RegisterClass);
X86::VR128RegisterClass, dl);
SDValue Val = DAG.getCopyFromReg(Chain, dl, VReg, MVT::v4f32);
SaveXMMOps.push_back(Val);
}

84
test/CodeGen/X86/dbg-live-in-location.ll Normal file
View File

@ -0,0 +1,84 @@
; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:64:64:64-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f32:32:32-f64:64:64-v64:64:64-v128:128:128-a0:0:64-s0:64:64-f80:128:128-n8:16:32:64"
target triple = "x86_64-apple-darwin10.0.0"
@str = internal constant [3 x i8] c"Hi\00"
define void @foo() nounwind ssp {
entry:
%puts = tail call i32 @puts(i8* getelementptr inbounds ([3 x i8]* @str, i64 0, i64 0))
ret void, !dbg !17
}
; CHECK: arg.c:5:14
define i32 @main(i32 %argc, i8** nocapture %argv) nounwind ssp {
entry:
tail call void @llvm.dbg.value(metadata !{i32 %argc}, i64 0, metadata !9), !dbg !19
tail call void @llvm.dbg.value(metadata !{i8** %argv}, i64 0, metadata !10), !dbg !20
%cmp = icmp sgt i32 %argc, 1, !dbg !21
br i1 %cmp, label %cond.end, label %for.body.lr.ph, !dbg !21
cond.end: ; preds = %entry
%arrayidx = getelementptr inbounds i8** %argv, i64 1, !dbg !21
%tmp2 = load i8** %arrayidx, align 8, !dbg !21, !tbaa !22
%call = tail call i32 (...)* @atoi(i8* %tmp2) nounwind, !dbg !21
tail call void @llvm.dbg.value(metadata !{i32 %call}, i64 0, metadata !16), !dbg !21
tail call void @llvm.dbg.value(metadata !25, i64 0, metadata !14), !dbg !26
%cmp57 = icmp sgt i32 %call, 0, !dbg !26
br i1 %cmp57, label %for.body.lr.ph, label %for.end, !dbg !26
for.body.lr.ph: ; preds = %entry, %cond.end
%cond10 = phi i32 [ %call, %cond.end ], [ 300, %entry ]
br label %for.body
for.body: ; preds = %for.body, %for.body.lr.ph
%i.08 = phi i32 [ 0, %for.body.lr.ph ], [ %inc, %for.body ]
%puts.i = tail call i32 @puts(i8* getelementptr inbounds ([3 x i8]* @str, i64 0, i64 0)) nounwind
%inc = add nsw i32 %i.08, 1, !dbg !27
%exitcond = icmp eq i32 %inc, %cond10
br i1 %exitcond, label %for.end, label %for.body, !dbg !26
for.end: ; preds = %for.body, %cond.end
ret i32 0, !dbg !29
}
declare i32 @atoi(...)
declare void @llvm.dbg.value(metadata, i64, metadata) nounwind readnone
declare i32 @puts(i8* nocapture) nounwind
!llvm.dbg.sp = !{!0, !5}
!llvm.dbg.lv.main = !{!9, !10, !14, !16}
!0 = metadata !{i32 589870, i32 0, metadata !1, metadata !"foo", metadata !"foo", metadata !"", metadata !1, i32 2, metadata !3, i1 false, i1 true, i32 0, i32 0, i32 0, i32 0, i1 true, void ()* @foo} ; [ DW_TAG_subprogram ]
!1 = metadata !{i32 589865, metadata !"arg.c", metadata !"/private/tmp", metadata !2} ; [ DW_TAG_file_type ]
!2 = metadata !{i32 589841, i32 0, i32 12, metadata !"arg.c", metadata !"/private/tmp", metadata !"clang version 2.9 (trunk 124504)", i1 true, i1 true, metadata !"", i32 0} ; [ DW_TAG_compile_unit ]
!3 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !4, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
!4 = metadata !{null}
!5 = metadata !{i32 589870, i32 0, metadata !1, metadata !"main", metadata !"main", metadata !"", metadata !1, i32 6, metadata !6, i1 false, i1 true, i32 0, i32 0, i32 0, i32 256, i1 true, i32 (i32, i8**)* @main} ; [ DW_TAG_subprogram ]
!6 = metadata !{i32 589845, metadata !1, metadata !"", metadata !1, i32 0, i64 0, i64 0, i32 0, i32 0, i32 0, metadata !7, i32 0, i32 0} ; [ DW_TAG_subroutine_type ]
!7 = metadata !{metadata !8}
!8 = metadata !{i32 589860, metadata !2, metadata !"int", null, i32 0, i64 32, i64 32, i64 0, i32 0, i32 5} ; [ DW_TAG_base_type ]
!9 = metadata !{i32 590081, metadata !5, metadata !"argc", metadata !1, i32 5, metadata !8, i32 0} ; [ DW_TAG_arg_variable ]
!10 = metadata !{i32 590081, metadata !5, metadata !"argv", metadata !1, i32 5, metadata !11, i32 0} ; [ DW_TAG_arg_variable ]
!11 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !12} ; [ DW_TAG_pointer_type ]
!12 = metadata !{i32 589839, metadata !2, metadata !"", null, i32 0, i64 64, i64 64, i64 0, i32 0, metadata !13} ; [ DW_TAG_pointer_type ]
!13 = metadata !{i32 589860, metadata !2, metadata !"char", null, i32 0, i64 8, i64 8, i64 0, i32 0, i32 6} ; [ DW_TAG_base_type ]
!14 = metadata !{i32 590080, metadata !15, metadata !"i", metadata !1, i32 7, metadata !8, i32 0} ; [ DW_TAG_auto_variable ]
!15 = metadata !{i32 589835, metadata !5, i32 6, i32 1, metadata !1, i32 1} ; [ DW_TAG_lexical_block ]
!16 = metadata !{i32 590080, metadata !15, metadata !"iterations", metadata !1, i32 8, metadata !8, i32 0} ; [ DW_TAG_auto_variable ]
!17 = metadata !{i32 4, i32 1, metadata !18, null}
!18 = metadata !{i32 589835, metadata !0, i32 2, i32 12, metadata !1, i32 0} ; [ DW_TAG_lexical_block ]
!19 = metadata !{i32 5, i32 14, metadata !5, null}
!20 = metadata !{i32 5, i32 26, metadata !5, null}
!21 = metadata !{i32 8, i32 51, metadata !15, null}
!22 = metadata !{metadata !"any pointer", metadata !23}
!23 = metadata !{metadata !"omnipotent char", metadata !24}
!24 = metadata !{metadata !"Simple C/C++ TBAA", null}
!25 = metadata !{i32 0}
!26 = metadata !{i32 9, i32 2, metadata !15, null}
!27 = metadata !{i32 9, i32 30, metadata !28, null}
!28 = metadata !{i32 589835, metadata !15, i32 9, i32 2, metadata !1, i32 2} ; [ DW_TAG_lexical_block ]
!29 = metadata !{i32 12, i32 9, metadata !15, null}