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https://github.com/c64scene-ar/llvm-6502.git
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Add left shift
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@70747 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -68,6 +68,7 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
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setTruncStoreAction(MVT::i16, MVT::i8, Expand);
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setOperationAction(ISD::SRA, MVT::i16, Custom);
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setOperationAction(ISD::SHL, MVT::i16, Custom);
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setOperationAction(ISD::RET, MVT::Other, Custom);
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setOperationAction(ISD::GlobalAddress, MVT::i16, Custom);
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setOperationAction(ISD::BR_CC, MVT::Other, Expand);
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@ -82,6 +83,7 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) :
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SDValue MSP430TargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
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switch (Op.getOpcode()) {
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case ISD::FORMAL_ARGUMENTS: return LowerFORMAL_ARGUMENTS(Op, DAG);
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case ISD::SHL: // FALLTHROUGH
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case ISD::SRA: return LowerShifts(Op, DAG);
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case ISD::RET: return LowerRET(Op, DAG);
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case ISD::CALL: return LowerCALL(Op, DAG);
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@ -416,12 +418,14 @@ MSP430TargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
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SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
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SelectionDAG &DAG) {
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assert(Op.getOpcode() == ISD::SRA && "Only SRA is currently supported.");
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unsigned Opc = Op.getOpcode();
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assert((Opc == ISD::SRA || ISD::SHL) &&
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"Only SRA and SHL are currently supported.");
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SDNode* N = Op.getNode();
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MVT VT = Op.getValueType();
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DebugLoc dl = N->getDebugLoc();
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// We currently only lower SRA of constant argument.
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// We currently only lower shifts of constant argument.
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if (!isa<ConstantSDNode>(N->getOperand(1)))
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return SDValue();
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@ -432,7 +436,8 @@ SDValue MSP430TargetLowering::LowerShifts(SDValue Op,
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// E.g.: foo >> (8 + N) => sxt(swpb(foo)) >> N
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SDValue Victim = N->getOperand(0);
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while (ShiftAmount--)
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Victim = DAG.getNode(MSP430ISD::RRA, dl, VT, Victim);
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Victim = DAG.getNode((Opc == ISD::SRA ? MSP430ISD::RRA : MSP430ISD::RLA),
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dl, VT, Victim);
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return Victim;
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}
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@ -560,6 +565,7 @@ const char *MSP430TargetLowering::getTargetNodeName(unsigned Opcode) const {
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default: return NULL;
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case MSP430ISD::RET_FLAG: return "MSP430ISD::RET_FLAG";
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case MSP430ISD::RRA: return "MSP430ISD::RRA";
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case MSP430ISD::RLA: return "MSP430ISD::RRA";
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case MSP430ISD::CALL: return "MSP430ISD::CALL";
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case MSP430ISD::Wrapper: return "MSP430ISD::Wrapper";
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case MSP430ISD::BRCOND: return "MSP430ISD::BRCOND";
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@ -27,8 +27,8 @@ namespace llvm {
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/// Return with a flag operand. Operand 0 is the chain operand.
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RET_FLAG,
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/// Y = RRA X, rotate right arithmetically
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RRA,
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/// Y = R{R,L}A X, rotate right (left) arithmetically
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RRA, RLA,
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/// CALL/TAILCALL - These operations represent an abstract call
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/// instruction, which includes a bunch of information.
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@ -41,6 +41,7 @@ def MSP430retflag : SDNode<"MSP430ISD::RET_FLAG", SDTNone,
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[SDNPHasChain, SDNPOptInFlag]>;
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def MSP430rra : SDNode<"MSP430ISD::RRA", SDTIntUnaryOp, []>;
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def MSP430rla : SDNode<"MSP430ISD::RLA", SDTIntUnaryOp, []>;
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def MSP430call : SDNode<"MSP430ISD::CALL", SDT_MSP430Call,
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[SDNPHasChain, SDNPOutFlag, SDNPOptInFlag]>;
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@ -591,6 +592,11 @@ def SAR16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
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[(set GR16:$dst, (MSP430rra GR16:$src)),
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(implicit SRW)]>;
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def SHL16r1 : Pseudo<(outs GR16:$dst), (ins GR16:$src),
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"rla.w\t$dst",
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[(set GR16:$dst, (MSP430rla GR16:$src)),
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(implicit SRW)]>;
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def SEXT16r : Pseudo<(outs GR16:$dst), (ins GR16:$src),
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"sxt\t$dst",
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[(set GR16:$dst, (sext_inreg GR16:$src, i8)),
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