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Implement and_sext.ll:test3, generating:
_test4: srawi r3, r3, 16 blr instead of: _test4: srwi r2, r3, 16 extsh r3, r2 blr for: short test4(unsigned X) { return (X >> 16); } git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@28174 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1936,7 +1936,7 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
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unsigned EVTBits = MVT::getSizeInBits(EVT);
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// fold (sext_in_reg c1) -> c1
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if (isa<ConstantSDNode>(N0))
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if (isa<ConstantSDNode>(N0) || N0.getOpcode() == ISD::UNDEF)
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return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0, N1);
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// If the input is already sign extended, just drop the extension.
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@ -1949,6 +1949,13 @@ SDOperand DAGCombiner::visitSIGN_EXTEND_INREG(SDNode *N) {
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return DAG.getNode(ISD::SIGN_EXTEND_INREG, VT, N0.getOperand(0), N1);
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}
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// fold (sext_in_reg (srl X, 24), i8) -> sra X, 24
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if (N0.getOpcode() == ISD::SRL) {
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if (ConstantSDNode *ShAmt = dyn_cast<ConstantSDNode>(N0.getOperand(1)))
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if (ShAmt->getValue()+EVTBits == MVT::getSizeInBits(VT))
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return DAG.getNode(ISD::SRA, VT, N0.getOperand(0), N0.getOperand(1));
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}
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// fold (sext_in_reg x) -> (zext_in_reg x) if the sign bit is zero
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if (TLI.MaskedValueIsZero(N0, 1ULL << (EVTBits-1)))
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return DAG.getZeroExtendInReg(N0, EVT);
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