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[X86] Improved tablegen patters for matching TZCNT/LZCNT.
Teach ISel how to match a TZCNT/LZCNT from a conditional move if the condition code is X86_COND_NE. Existing tablegen patterns only allowed to match TZCNT/LZCNT from a X86cond with condition code equal to X86_COND_E. To avoid introducing extra rules, I added an 'ImmLeaf' definition that checks if the condition code is COND_E or COND_NE. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@223668 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Andrea Di Biagio
parent
cf2daa3671
commit
eafdf26d89
@ -803,6 +803,11 @@ def X86_COND_O : PatLeaf<(i8 13)>;
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def X86_COND_P : PatLeaf<(i8 14)>; // alt. COND_PE
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def X86_COND_S : PatLeaf<(i8 15)>;
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// Predicate used to help when pattern matching LZCNT/TZCNT.
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def X86_COND_E_OR_NE : ImmLeaf<i8, [{
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return (Imm == X86::COND_E) || (Imm == X86::COND_NE);
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}]>;
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let FastIselShouldIgnore = 1 in { // FastIsel should ignore all simm8 instrs.
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def i16immSExt8 : ImmLeaf<i16, [{ return Imm == (int8_t)Imm; }]>;
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def i32immSExt8 : ImmLeaf<i32, [{ return Imm == (int8_t)Imm; }]>;
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@ -1981,41 +1986,41 @@ let Predicates = [HasLZCNT], Defs = [EFLAGS] in {
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}
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let Predicates = [HasLZCNT] in {
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def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E),
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def : Pat<(X86cmov (ctlz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
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(X86cmp GR16:$src, (i16 0))),
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(LZCNT16rr GR16:$src)>;
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def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E),
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def : Pat<(X86cmov (ctlz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
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(X86cmp GR32:$src, (i32 0))),
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(LZCNT32rr GR32:$src)>;
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def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E),
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def : Pat<(X86cmov (ctlz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
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(X86cmp GR64:$src, (i64 0))),
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(LZCNT64rr GR64:$src)>;
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def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E),
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def : Pat<(X86cmov (i16 16), (ctlz GR16:$src), (X86_COND_E_OR_NE),
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(X86cmp GR16:$src, (i16 0))),
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(LZCNT16rr GR16:$src)>;
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def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E),
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def : Pat<(X86cmov (i32 32), (ctlz GR32:$src), (X86_COND_E_OR_NE),
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(X86cmp GR32:$src, (i32 0))),
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(LZCNT32rr GR32:$src)>;
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def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E),
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def : Pat<(X86cmov (i64 64), (ctlz GR64:$src), (X86_COND_E_OR_NE),
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(X86cmp GR64:$src, (i64 0))),
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(LZCNT64rr GR64:$src)>;
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def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E),
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def : Pat<(X86cmov (ctlz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
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(X86cmp (loadi16 addr:$src), (i16 0))),
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(LZCNT16rm addr:$src)>;
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def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E),
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def : Pat<(X86cmov (ctlz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
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(X86cmp (loadi32 addr:$src), (i32 0))),
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(LZCNT32rm addr:$src)>;
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def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E),
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def : Pat<(X86cmov (ctlz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
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(X86cmp (loadi64 addr:$src), (i64 0))),
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(LZCNT64rm addr:$src)>;
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def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E),
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def : Pat<(X86cmov (i16 16), (ctlz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
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(X86cmp (loadi16 addr:$src), (i16 0))),
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(LZCNT16rm addr:$src)>;
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def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E),
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def : Pat<(X86cmov (i32 32), (ctlz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
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(X86cmp (loadi32 addr:$src), (i32 0))),
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(LZCNT32rm addr:$src)>;
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def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E),
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def : Pat<(X86cmov (i64 64), (ctlz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
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(X86cmp (loadi64 addr:$src), (i64 0))),
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(LZCNT64rm addr:$src)>;
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}
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@ -2097,41 +2102,41 @@ let Predicates = [HasBMI] in {
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}
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let Predicates = [HasBMI] in {
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def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E),
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def : Pat<(X86cmov (cttz GR16:$src), (i16 16), (X86_COND_E_OR_NE),
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(X86cmp GR16:$src, (i16 0))),
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(TZCNT16rr GR16:$src)>;
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def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E),
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def : Pat<(X86cmov (cttz GR32:$src), (i32 32), (X86_COND_E_OR_NE),
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(X86cmp GR32:$src, (i32 0))),
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(TZCNT32rr GR32:$src)>;
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def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E),
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def : Pat<(X86cmov (cttz GR64:$src), (i64 64), (X86_COND_E_OR_NE),
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(X86cmp GR64:$src, (i64 0))),
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(TZCNT64rr GR64:$src)>;
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def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E),
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def : Pat<(X86cmov (i16 16), (cttz GR16:$src), (X86_COND_E_OR_NE),
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(X86cmp GR16:$src, (i16 0))),
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(TZCNT16rr GR16:$src)>;
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def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E),
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def : Pat<(X86cmov (i32 32), (cttz GR32:$src), (X86_COND_E_OR_NE),
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(X86cmp GR32:$src, (i32 0))),
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(TZCNT32rr GR32:$src)>;
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def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E),
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def : Pat<(X86cmov (i64 64), (cttz GR64:$src), (X86_COND_E_OR_NE),
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(X86cmp GR64:$src, (i64 0))),
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(TZCNT64rr GR64:$src)>;
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def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E),
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def : Pat<(X86cmov (cttz (loadi16 addr:$src)), (i16 16), (X86_COND_E_OR_NE),
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(X86cmp (loadi16 addr:$src), (i16 0))),
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(TZCNT16rm addr:$src)>;
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def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E),
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def : Pat<(X86cmov (cttz (loadi32 addr:$src)), (i32 32), (X86_COND_E_OR_NE),
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(X86cmp (loadi32 addr:$src), (i32 0))),
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(TZCNT32rm addr:$src)>;
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def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E),
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def : Pat<(X86cmov (cttz (loadi64 addr:$src)), (i64 64), (X86_COND_E_OR_NE),
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(X86cmp (loadi64 addr:$src), (i64 0))),
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(TZCNT64rm addr:$src)>;
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def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E),
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def : Pat<(X86cmov (i16 16), (cttz (loadi16 addr:$src)), (X86_COND_E_OR_NE),
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(X86cmp (loadi16 addr:$src), (i16 0))),
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(TZCNT16rm addr:$src)>;
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def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E),
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def : Pat<(X86cmov (i32 32), (cttz (loadi32 addr:$src)), (X86_COND_E_OR_NE),
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(X86cmp (loadi32 addr:$src), (i32 0))),
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(TZCNT32rm addr:$src)>;
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def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E),
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def : Pat<(X86cmov (i64 64), (cttz (loadi64 addr:$src)), (X86_COND_E_OR_NE),
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(X86cmp (loadi64 addr:$src), (i64 0))),
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(TZCNT64rm addr:$src)>;
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}
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@ -437,6 +437,137 @@ define i64 @test18_cttz(i64* %ptr) {
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; CHECK: tzcnt
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; CHECK-NEXT: ret
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define i16 @test1b_ctlz(i16 %v) {
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%cnt = tail call i16 @llvm.ctlz.i16(i16 %v, i1 true)
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%tobool = icmp ne i16 %v, 0
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%cond = select i1 %tobool, i16 16, i16 %cnt
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ret i16 %cond
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}
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; CHECK-LABEL: test1b_ctlz
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; CHECK: lzcnt
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; CHECK-NEXT: ret
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define i32 @test2b_ctlz(i32 %v) {
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%cnt = tail call i32 @llvm.ctlz.i32(i32 %v, i1 true)
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%tobool = icmp ne i32 %v, 0
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%cond = select i1 %tobool, i32 32, i32 %cnt
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ret i32 %cond
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}
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; CHECK-LABEL: test2b_ctlz
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; CHECK: lzcnt
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; CHECK-NEXT: ret
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define i64 @test3b_ctlz(i64 %v) {
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%cnt = tail call i64 @llvm.ctlz.i64(i64 %v, i1 true)
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%tobool = icmp ne i64 %v, 0
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%cond = select i1 %tobool, i64 64, i64 %cnt
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ret i64 %cond
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}
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; CHECK-LABEL: test3b_ctlz
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; CHECK: lzcnt
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; CHECK-NEXT: ret
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define i16 @test4b_ctlz(i16 %v) {
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%cnt = tail call i16 @llvm.ctlz.i16(i16 %v, i1 true)
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%tobool = icmp ne i16 %v, 0
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%cond = select i1 %tobool, i16 %cnt, i16 16
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ret i16 %cond
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}
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; CHECK-LABEL: test4b_ctlz
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; CHECK: lzcnt
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; CHECK-NEXT: ret
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define i32 @test5b_ctlz(i32 %v) {
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%cnt = tail call i32 @llvm.ctlz.i32(i32 %v, i1 true)
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%tobool = icmp ne i32 %v, 0
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%cond = select i1 %tobool, i32 %cnt, i32 32
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ret i32 %cond
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}
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; CHECK-LABEL: test5b_ctlz
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; CHECK: lzcnt
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; CHECK-NEXT: ret
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define i64 @test6b_ctlz(i64 %v) {
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%cnt = tail call i64 @llvm.ctlz.i64(i64 %v, i1 true)
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%tobool = icmp ne i64 %v, 0
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%cond = select i1 %tobool, i64 %cnt, i64 64
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ret i64 %cond
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}
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; CHECK-LABEL: test6b_ctlz
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; CHECK: lzcnt
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; CHECK-NEXT: ret
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define i16 @test1b_cttz(i16 %v) {
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%cnt = tail call i16 @llvm.cttz.i16(i16 %v, i1 true)
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%tobool = icmp ne i16 %v, 0
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%cond = select i1 %tobool, i16 16, i16 %cnt
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ret i16 %cond
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}
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; CHECK-LABEL: test1b_cttz
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; CHECK: tzcnt
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; CHECK-NEXT: ret
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define i32 @test2b_cttz(i32 %v) {
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%cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true)
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%tobool = icmp ne i32 %v, 0
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%cond = select i1 %tobool, i32 32, i32 %cnt
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ret i32 %cond
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}
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; CHECK-LABEL: test2b_cttz
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; CHECK: tzcnt
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; CHECK-NEXT: ret
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define i64 @test3b_cttz(i64 %v) {
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%cnt = tail call i64 @llvm.cttz.i64(i64 %v, i1 true)
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%tobool = icmp ne i64 %v, 0
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%cond = select i1 %tobool, i64 64, i64 %cnt
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ret i64 %cond
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}
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; CHECK-LABEL: test3b_cttz
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; CHECK: tzcnt
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; CHECK-NEXT: ret
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define i16 @test4b_cttz(i16 %v) {
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%cnt = tail call i16 @llvm.cttz.i16(i16 %v, i1 true)
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%tobool = icmp ne i16 %v, 0
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%cond = select i1 %tobool, i16 %cnt, i16 16
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ret i16 %cond
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}
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; CHECK-LABEL: test4b_cttz
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; CHECK: tzcnt
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; CHECK-NEXT: ret
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define i32 @test5b_cttz(i32 %v) {
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%cnt = tail call i32 @llvm.cttz.i32(i32 %v, i1 true)
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%tobool = icmp ne i32 %v, 0
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%cond = select i1 %tobool, i32 %cnt, i32 32
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ret i32 %cond
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}
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; CHECK-LABEL: test5b_cttz
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; CHECK: tzcnt
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; CHECK-NEXT: ret
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define i64 @test6b_cttz(i64 %v) {
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%cnt = tail call i64 @llvm.cttz.i64(i64 %v, i1 true)
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%tobool = icmp ne i64 %v, 0
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%cond = select i1 %tobool, i64 %cnt, i64 64
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ret i64 %cond
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}
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; CHECK-LABEL: test6b_cttz
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; CHECK: tzcnt
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; CHECK-NEXT: ret
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declare i64 @llvm.cttz.i64(i64, i1)
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declare i32 @llvm.cttz.i32(i32, i1)
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