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Merging r228189:
------------------------------------------------------------------------ r228189 | thomas.stellard | 2015-02-04 15:49:51 -0500 (Wed, 04 Feb 2015) | 9 lines R600/SI: Make more store operations legal v2i32, i32, trunc i32 to i16, and truc i32 to i8 stores are legal for all address spaces. We had marked them as custom in order to lower them for the private address space, but this is no longer necessary. This enables lowering of misaligned stores of these types in the DAGLegalizer. ------------------------------------------------------------------------ git-svn-id: https://llvm.org/svn/llvm-project/llvm/branches/release_36@235339 91177308-0d34-0410-b5e6-96231b3b80d8
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Tom Stellard committed
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@@ -159,9 +159,6 @@ AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) :
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// Custom lowering of vector stores is required for local address space
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// stores.
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setOperationAction(ISD::STORE, MVT::v4i32, Custom);
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// XXX: Native v2i32 local address space stores are possible, but not
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// currently implemented.
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setOperationAction(ISD::STORE, MVT::v2i32, Custom);
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setTruncStoreAction(MVT::v2i32, MVT::v2i16, Custom);
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setTruncStoreAction(MVT::v2i32, MVT::v2i8, Custom);
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@@ -89,8 +89,6 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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setOperationAction(ISD::STORE, MVT::v16i32, Custom);
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setOperationAction(ISD::STORE, MVT::i1, Custom);
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setOperationAction(ISD::STORE, MVT::i32, Custom);
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setOperationAction(ISD::STORE, MVT::v2i32, Custom);
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setOperationAction(ISD::STORE, MVT::v4i32, Custom);
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setOperationAction(ISD::SELECT, MVT::i64, Custom);
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@@ -158,8 +156,6 @@ SITargetLowering::SITargetLowering(TargetMachine &TM) :
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for (MVT VT : MVT::fp_valuetypes())
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setLoadExtAction(ISD::EXTLOAD, VT, MVT::f32, Expand);
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setTruncStoreAction(MVT::i32, MVT::i8, Custom);
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setTruncStoreAction(MVT::i32, MVT::i16, Custom);
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setTruncStoreAction(MVT::f64, MVT::f32, Expand);
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setTruncStoreAction(MVT::i64, MVT::i32, Expand);
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setTruncStoreAction(MVT::v8i32, MVT::v8i16, Expand);
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@@ -1125,11 +1121,6 @@ SDValue SITargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
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EVT VT = Store->getMemoryVT();
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// These stores are legal.
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if (Store->getAddressSpace() == AMDGPUAS::LOCAL_ADDRESS &&
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VT.isVector() && VT.getVectorNumElements() == 2 &&
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VT.getVectorElementType() == MVT::i32)
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return SDValue();
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if (Store->getAddressSpace() == AMDGPUAS::PRIVATE_ADDRESS) {
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if (VT.isVector() && VT.getVectorNumElements() > 4)
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return ScalarizeVectorStore(Op, DAG);
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@@ -6,7 +6,10 @@
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_write_b32
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: s_endpgm
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define void @unaligned_load_store_i32_local(i32 addrspace(3)* %p, i32 addrspace(3)* %r) nounwind {
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%v = load i32 addrspace(3)* %p, align 1
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@@ -19,7 +22,10 @@ define void @unaligned_load_store_i32_local(i32 addrspace(3)* %p, i32 addrspace(
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; SI: buffer_load_ubyte
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; SI: buffer_load_ubyte
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; SI: buffer_load_ubyte
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; SI: buffer_store_dword
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; SI: buffer_store_byte
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; SI: buffer_store_byte
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; SI: buffer_store_byte
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; SI: buffer_store_byte
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define void @unaligned_load_store_i32_global(i32 addrspace(1)* %p, i32 addrspace(1)* %r) nounwind {
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%v = load i32 addrspace(1)* %p, align 1
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store i32 %v, i32 addrspace(1)* %r, align 1
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@@ -35,8 +41,14 @@ define void @unaligned_load_store_i32_global(i32 addrspace(1)* %p, i32 addrspace
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_write_b32
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; SI: ds_write_b32
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: s_endpgm
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define void @unaligned_load_store_i64_local(i64 addrspace(3)* %p, i64 addrspace(3)* %r) {
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%v = load i64 addrspace(3)* %p, align 1
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@@ -53,8 +65,14 @@ define void @unaligned_load_store_i64_local(i64 addrspace(3)* %p, i64 addrspace(
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; SI: buffer_load_ubyte
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; SI: buffer_load_ubyte
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; SI: buffer_load_ubyte
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; SI: buffer_store_dword
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; SI: buffer_store_dword
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; SI: buffer_store_byte
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; SI: buffer_store_byte
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; SI: buffer_store_byte
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; SI: buffer_store_byte
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; SI: buffer_store_byte
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; SI: buffer_store_byte
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; SI: buffer_store_byte
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; SI: buffer_store_byte
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define void @unaligned_load_store_i64_global(i64 addrspace(1)* %p, i64 addrspace(1)* %r) {
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%v = load i64 addrspace(1)* %p, align 1
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store i64 %v, i64 addrspace(1)* %r, align 1
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@@ -82,10 +100,25 @@ define void @unaligned_load_store_i64_global(i64 addrspace(1)* %p, i64 addrspace
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_write_b32
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; SI: ds_write_b32
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; SI: ds_write_b32
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; SI: ds_write_b32
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: ds_write_b8
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; SI: s_endpgm
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define void @unaligned_load_store_v4i32_local(<4 x i32> addrspace(3)* %p, <4 x i32> addrspace(3)* %r) nounwind {
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%v = load <4 x i32> addrspace(3)* %p, align 1
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@@ -149,12 +182,23 @@ define void @load_lds_i64_align_4_with_split_offset(i64 addrspace(1)* nocapture
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ret void
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}
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; FIXME: Need to fix this case.
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; define void @load_lds_i64_align_1(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
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; %val = load i64 addrspace(3)* %in, align 1
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; store i64 %val, i64 addrspace(1)* %out, align 8
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; ret void
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; }
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; SI-LABEL: {{^}}load_lds_i64_align_1:
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: ds_read_u8
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; SI: buffer_store_dwordx2
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; SI: s_endpgm
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define void @load_lds_i64_align_1(i64 addrspace(1)* nocapture %out, i64 addrspace(3)* %in) #0 {
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%val = load i64 addrspace(3)* %in, align 1
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store i64 %val, i64 addrspace(1)* %out, align 8
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ret void
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}
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; SI-LABEL: {{^}}store_lds_i64_align_4:
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; SI: ds_write2_b32
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