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implementation of some methods for inlineasm

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@25951 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Chris Lattner 2006-02-04 02:13:02 +00:00
parent c991cf58aa
commit eb8146b5ee
1 changed files with 41 additions and 1 deletions
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42
lib/CodeGen/SelectionDAG/TargetLowering.cpp
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@ -131,6 +131,10 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
return NULL;
}
//===----------------------------------------------------------------------===//
// Optimization Methods
//===----------------------------------------------------------------------===//
/// DemandedBitsAreZero - Return true if 'Op & Mask' demands no bits from a bit
/// set operation such as a sign extend or or/xor with constant whose only
/// use is Op. If it returns true, the old node that sets bits which are
@ -139,7 +143,7 @@ const char *TargetLowering::getTargetNodeName(unsigned Opcode) const {
/// desired.
bool TargetLowering::DemandedBitsAreZero(const SDOperand &Op, uint64_t Mask,
SDOperand &Old, SDOperand &New,
SelectionDAG &DAG) {
SelectionDAG &DAG) const {
// If the operation has more than one use, we're not interested in it.
// Tracking down and checking all uses would be problematic and slow.
if (!Op.Val->hasOneUse())
@ -302,6 +306,42 @@ bool TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op,
return false;
}
//===----------------------------------------------------------------------===//
// Inline Assembler Implementation Methods
//===----------------------------------------------------------------------===//
TargetLowering::ConstraintType
TargetLowering::getConstraintType(char ConstraintLetter) const {
// FIXME: lots more standard ones to handle.
switch (ConstraintLetter) {
default: return C_Unknown;
case 'r': return C_RegisterClass;
case 'i': // Simple Integer or Relocatable Constant
case 'n': // Simple Integer
case 's': // Relocatable Constant
case 'I': // Target registers.
case 'J':
case 'K':
case 'L':
case 'M':
case 'N':
case 'O':
case 'P': return C_Other;
}
}
bool TargetLowering::isOperandValidForConstraint(SDOperand Op,
char ConstraintLetter) {
switch (ConstraintLetter) {
default: return false;
case 'i': // Simple Integer or Relocatable Constant
case 'n': // Simple Integer
case 's': // Relocatable Constant
return true; // FIXME: not right.
}
}
std::vector<unsigned> TargetLowering::
getRegForInlineAsmConstraint(const std::string &Constraint) const {
// Not a physreg, must not be a register reference or something.