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[AArch64] Fix problems in decoding generic MSR instructions

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Bitpatterns rejected by the decoder method of `MSR (immediate)` should be
decoded as the `extended MSR (register)` instruction.

Differential Revision: http://reviews.llvm.org/D7174


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@242276 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Petr Pavlu 2015-07-15 08:10:30 +00:00
parent f31b1ec106
commit ec223f1217
2 changed files with 7 additions and 0 deletions
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3
lib/Target/AArch64/AArch64InstrFormats.td
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@ -913,6 +913,9 @@ class MSRpstateI
let Inst{7-5} = pstatefield{2-0};
let DecoderMethod = "DecodeSystemPStateInstruction";
// MSRpstateI aliases with MSRI. When the MSRpstateI decoder method returns
// Fail the decoder should attempt to decode the instruction as MSRI.
let hasCompleteDecoder = 0;
}
// SYS and SYSL generic system instructions.

4
test/MC/Disassembler/AArch64/basic-a64-instructions.txt
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@ -4172,12 +4172,16 @@
# CHECK: mrs x12, {{s3_7_c15_c1_5|S3_7_C15_C1_5}}
# CHECK: mrs x13, {{s3_2_c11_c15_7|S3_2_C11_C15_7}}
# CHECK: mrs xzr, {{s0_0_c4_c0_0|S0_0_C4_C0_0}}
# CHECK: msr {{s3_0_c15_c0_0|S3_0_C15_C0_0}}, x12
# CHECK: msr {{s3_7_c11_c13_7|S3_7_C11_C13_7}}, x5
# CHECK: msr {{s0_0_c4_c0_0|S0_0_C4_C0_0}}, xzr
0xac 0xf1 0x3f 0xd5
0xed 0xbf 0x3a 0xd5
0x1f 0x40 0x20 0xd5
0x0c 0xf0 0x18 0xd5
0xe5 0xbd 0x1f 0xd5
0x1f 0x40 0x00 0xd5
#------------------------------------------------------------------------------
# Test and branch (immediate)