mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
Fix Whitespace.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@116173 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Michael J. Spencer
parent
27287664c2
commit
ec38de2ca8
@ -64,7 +64,7 @@ public:
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bool WriteNopData(uint64_t Count, MCObjectWriter *OW) const;
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};
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} // end anonymous namespace
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} // end anonymous namespace
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static unsigned getRelaxedOpcode(unsigned Op) {
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switch (Op) {
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@ -345,7 +345,7 @@ public:
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}
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};
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} // end anonymous namespace
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} // end anonymous namespace
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TargetAsmBackend *llvm::createX86_32AsmBackend(const Target &T,
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const std::string &TT) {
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@ -63,9 +63,9 @@ static SDValue getMOVL(SelectionDAG &DAG, DebugLoc dl, EVT VT, SDValue V1,
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SDValue V2);
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static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
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bool is64Bit = TM.getSubtarget<X86Subtarget>().is64Bit();
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if (TM.getSubtarget<X86Subtarget>().isTargetDarwin()) {
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if (is64Bit) return new X8664_MachoTargetObjectFile();
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return new TargetLoweringObjectFileMachO();
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@ -74,7 +74,7 @@ static TargetLoweringObjectFile *createTLOF(X86TargetMachine &TM) {
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return new X8632_ELFTargetObjectFile(TM);
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} else if (TM.getSubtarget<X86Subtarget>().isTargetCOFF()) {
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return new TargetLoweringObjectFileCOFF();
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}
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}
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llvm_unreachable("unknown subtarget type");
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}
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@ -213,7 +213,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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}
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// TODO: when we have SSE, these could be more efficient, by using movd/movq.
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if (!X86ScalarSSEf64) {
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if (!X86ScalarSSEf64) {
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setOperationAction(ISD::BIT_CONVERT , MVT::f32 , Expand);
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setOperationAction(ISD::BIT_CONVERT , MVT::i32 , Expand);
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if (Subtarget->is64Bit()) {
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@ -343,7 +343,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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// We may not have a libcall for MEMBARRIER so we should lower this.
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setOperationAction(ISD::MEMBARRIER , MVT::Other, Custom);
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// On X86 and X86-64, atomic operations are lowered to locked instructions.
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// Locked instructions, in turn, have implicit fence semantics (all memory
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// operations are flushed before issuing the locked instruction, and they
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@ -745,7 +745,7 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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// Do not attempt to promote non-128-bit vectors
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if (!VT.is128BitVector())
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continue;
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setOperationAction(ISD::AND, SVT, Promote);
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AddPromotedToType (ISD::AND, SVT, MVT::v2i64);
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setOperationAction(ISD::OR, SVT, Promote);
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@ -1085,7 +1085,7 @@ unsigned X86TargetLowering::getJumpTableEncoding() const {
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if (getTargetMachine().getRelocationModel() == Reloc::PIC_ &&
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Subtarget->isPICStyleGOT())
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return MachineJumpTableInfo::EK_Custom32;
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// Otherwise, use the normal jump table encoding heuristics.
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return TargetLowering::getJumpTableEncoding();
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}
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@ -1212,7 +1212,7 @@ bool X86TargetLowering::getStackCookieLocation(unsigned &AddressSpace,
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#include "X86GenCallingConv.inc"
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bool
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bool
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X86TargetLowering::CanLowerReturn(CallingConv::ID CallConv, bool isVarArg,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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LLVMContext &Context) const {
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@ -1299,7 +1299,7 @@ X86TargetLowering::LowerReturn(SDValue Chain,
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}
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}
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}
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Chain = DAG.getCopyToReg(Chain, dl, VA.getLocReg(), ValToCopy, Flag);
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Flag = Chain.getValue(1);
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}
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@ -1313,7 +1313,7 @@ X86TargetLowering::LowerReturn(SDValue Chain,
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MachineFunction &MF = DAG.getMachineFunction();
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X86MachineFunctionInfo *FuncInfo = MF.getInfo<X86MachineFunctionInfo>();
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unsigned Reg = FuncInfo->getSRetReturnReg();
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assert(Reg &&
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assert(Reg &&
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"SRetReturnReg should have been set in LowerFormalArguments().");
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SDValue Val = DAG.getCopyFromReg(Chain, dl, Reg, getPointerTy());
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@ -1478,7 +1478,7 @@ CreateCopyOfByValArgument(SDValue Src, SDValue Dst, SDValue Chain,
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ISD::ArgFlagsTy Flags, SelectionDAG &DAG,
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DebugLoc dl) {
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SDValue SizeNode = DAG.getConstant(Flags.getByValSize(), MVT::i32);
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return DAG.getMemcpy(Chain, dl, Dst, Src, SizeNode, Flags.getByValAlign(),
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/*isVolatile*/false, /*AlwaysInline=*/true,
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MachinePointerInfo(), MachinePointerInfo());
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@ -2893,15 +2893,15 @@ bool X86::isPSHUFLWMask(ShuffleVectorSDNode *N) {
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static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
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bool hasSSSE3) {
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int i, e = VT.getVectorNumElements();
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// Do not handle v2i64 / v2f64 shuffles with palignr.
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if (e < 4 || !hasSSSE3)
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return false;
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for (i = 0; i != e; ++i)
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if (Mask[i] >= 0)
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break;
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// All undef, not a palignr.
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if (i == e)
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return false;
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@ -2912,13 +2912,13 @@ static bool isPALIGNRMask(const SmallVectorImpl<int> &Mask, EVT VT,
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bool NeedsUnary = false;
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int s = Mask[i] - i;
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// Check the rest of the elements to see if they are consecutive.
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for (++i; i != e; ++i) {
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int m = Mask[i];
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if (m < 0)
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if (m < 0)
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continue;
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Unary = Unary && (m < (int)e);
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NeedsUnary = NeedsUnary || (m < s);
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@ -3006,10 +3006,10 @@ bool X86::isMOVHLPSMask(ShuffleVectorSDNode *N) {
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/// <2, 3, 2, 3>
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bool X86::isMOVHLPS_v_undef_Mask(ShuffleVectorSDNode *N) {
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unsigned NumElems = N->getValueType(0).getVectorNumElements();
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if (NumElems != 4)
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return false;
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return isUndefOrEqual(N->getMaskElt(0), 2) &&
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isUndefOrEqual(N->getMaskElt(1), 3) &&
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isUndefOrEqual(N->getMaskElt(2), 2) &&
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@ -3979,7 +3979,7 @@ static SDValue getVShift(bool isLeft, EVT VT, SDValue SrcOp,
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SDValue
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X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
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SelectionDAG &DAG) const {
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// Check if the scalar load can be widened into a vector load. And if
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// the address is "base + cst" see if the cst can be "absorbed" into
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// the shuffle mask.
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@ -4047,12 +4047,12 @@ X86TargetLowering::LowerAsSplatVectorLoad(SDValue SrcOp, EVT VT, DebugLoc dl,
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return SDValue();
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}
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/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
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/// vector of type 'VT', see if the elements can be replaced by a single large
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/// EltsFromConsecutiveLoads - Given the initializing elements 'Elts' of a
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/// vector of type 'VT', see if the elements can be replaced by a single large
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/// load which has the same value as a build_vector whose operands are 'elts'.
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///
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/// Example: <load i32 *a, load i32 *a+4, undef, undef> -> zextload a
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///
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///
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/// FIXME: we'd also like to handle the case where the last elements are zero
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/// rather than undef via VZEXT_LOAD, but we do not detect that case today.
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/// There's even a handy isZeroNode for that purpose.
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@ -4060,16 +4060,16 @@ static SDValue EltsFromConsecutiveLoads(EVT VT, SmallVectorImpl<SDValue> &Elts,
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DebugLoc &DL, SelectionDAG &DAG) {
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EVT EltVT = VT.getVectorElementType();
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unsigned NumElems = Elts.size();
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LoadSDNode *LDBase = NULL;
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unsigned LastLoadedElt = -1U;
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// For each element in the initializer, see if we've found a load or an undef.
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// If we don't find an initial load element, or later load elements are
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// If we don't find an initial load element, or later load elements are
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// non-consecutive, bail out.
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for (unsigned i = 0; i < NumElems; ++i) {
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SDValue Elt = Elts[i];
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if (!Elt.getNode() ||
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(Elt.getOpcode() != ISD::UNDEF && !ISD::isNON_EXTLoad(Elt.getNode())))
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return SDValue();
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@ -4349,20 +4349,20 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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// Check for a build vector of consecutive loads.
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for (unsigned i = 0; i < NumElems; ++i)
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V[i] = Op.getOperand(i);
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// Check for elements which are consecutive loads.
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SDValue LD = EltsFromConsecutiveLoads(VT, V, dl, DAG);
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if (LD.getNode())
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return LD;
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// For SSE 4.1, use insertps to put the high elements into the low element.
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// For SSE 4.1, use insertps to put the high elements into the low element.
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if (getSubtarget()->hasSSE41()) {
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SDValue Result;
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if (Op.getOperand(0).getOpcode() != ISD::UNDEF)
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Result = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, VT, Op.getOperand(0));
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else
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Result = DAG.getUNDEF(VT);
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for (unsigned i = 1; i < NumElems; ++i) {
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if (Op.getOperand(i).getOpcode() == ISD::UNDEF) continue;
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Result = DAG.getNode(ISD::INSERT_VECTOR_ELT, dl, VT, Result,
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@ -4370,7 +4370,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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}
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return Result;
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}
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// Otherwise, expand into a number of unpckl*, start by extending each of
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// our (non-undef) elements to the full vector width with the element in the
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// bottom slot of the vector (which generates no code for SSE).
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@ -4396,7 +4396,7 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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if (V[i+EltStride].getOpcode() == ISD::UNDEF &&
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EltStride == NumElems/2)
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continue;
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V[i] = getUnpackl(DAG, dl, VT, V[i], V[i + EltStride]);
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}
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EltStride >>= 1;
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@ -5826,7 +5826,7 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const {
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SDValue
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X86TargetLowering::LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) const {
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DebugLoc dl = Op.getDebugLoc();
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if (Op.getValueType() == MVT::v1i64 &&
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Op.getOperand(0).getValueType() == MVT::i64)
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return DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v1i64, Op.getOperand(0));
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@ -6082,12 +6082,12 @@ static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
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const EVT PtrVT, TLSModel::Model model,
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bool is64Bit) {
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DebugLoc dl = GA->getDebugLoc();
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// Get the Thread Pointer, which is %gs:0 (32-bit) or %fs:0 (64-bit).
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Value *Ptr = Constant::getNullValue(Type::getInt8PtrTy(*DAG.getContext(),
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is64Bit ? 257 : 256));
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SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
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SDValue ThreadPointer = DAG.getLoad(PtrVT, dl, DAG.getEntryNode(),
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DAG.getIntPtrConstant(0),
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MachinePointerInfo(Ptr), false, false, 0);
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@ -6108,7 +6108,7 @@ static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
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// emit "addl x@ntpoff,%eax" (local exec) or "addl x@indntpoff,%eax" (initial
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// exec)
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SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
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SDValue TGA = DAG.getTargetGlobalAddress(GA->getGlobal(), dl,
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GA->getValueType(0),
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GA->getOffset(), OperandFlags);
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SDValue Offset = DAG.getNode(WrapperKind, dl, PtrVT, TGA);
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@ -6124,29 +6124,29 @@ static SDValue LowerToTLSExecModel(GlobalAddressSDNode *GA, SelectionDAG &DAG,
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SDValue
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X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
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GlobalAddressSDNode *GA = cast<GlobalAddressSDNode>(Op);
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const GlobalValue *GV = GA->getGlobal();
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if (Subtarget->isTargetELF()) {
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// TODO: implement the "local dynamic" model
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// TODO: implement the "initial exec"model for pic executables
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// If GV is an alias then use the aliasee for determining
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// thread-localness.
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if (const GlobalAlias *GA = dyn_cast<GlobalAlias>(GV))
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GV = GA->resolveAliasedGlobal(false);
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TLSModel::Model model
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TLSModel::Model model
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= getTLSModel(GV, getTargetMachine().getRelocationModel());
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switch (model) {
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case TLSModel::GeneralDynamic:
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case TLSModel::LocalDynamic: // not implemented
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if (Subtarget->is64Bit())
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return LowerToTLSGeneralDynamicModel64(GA, DAG, getPointerTy());
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return LowerToTLSGeneralDynamicModel32(GA, DAG, getPointerTy());
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case TLSModel::InitialExec:
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case TLSModel::LocalExec:
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return LowerToTLSExecModel(GA, DAG, getPointerTy(), model,
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@ -6157,7 +6157,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
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unsigned char OpFlag = 0;
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unsigned WrapperKind = Subtarget->isPICStyleRIPRel() ?
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X86ISD::WrapperRIP : X86ISD::Wrapper;
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// In PIC mode (unless we're in RIPRel PIC mode) we add an offset to the
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// global base reg.
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bool PIC32 = (getTargetMachine().getRelocationModel() == Reloc::PIC_) &&
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@ -6166,24 +6166,24 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
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OpFlag = X86II::MO_TLVP_PIC_BASE;
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else
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OpFlag = X86II::MO_TLVP;
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DebugLoc DL = Op.getDebugLoc();
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DebugLoc DL = Op.getDebugLoc();
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SDValue Result = DAG.getTargetGlobalAddress(GA->getGlobal(), DL,
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getPointerTy(),
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GA->getOffset(), OpFlag);
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SDValue Offset = DAG.getNode(WrapperKind, DL, getPointerTy(), Result);
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// With PIC32, the address is actually $g + Offset.
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if (PIC32)
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Offset = DAG.getNode(ISD::ADD, DL, getPointerTy(),
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DAG.getNode(X86ISD::GlobalBaseReg,
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DebugLoc(), getPointerTy()),
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Offset);
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// Lowering the machine isd will make sure everything is in the right
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// location.
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SDValue Args[] = { Offset };
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SDValue Chain = DAG.getNode(X86ISD::TLSCALL, DL, MVT::Other, Args, 1);
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// TLSCALL will be codegen'ed as call. Inform MFI that function has calls.
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MachineFrameInfo *MFI = DAG.getMachineFunction().getFrameInfo();
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MFI->setAdjustsStack(true);
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@ -6193,7 +6193,7 @@ X86TargetLowering::LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const {
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unsigned Reg = Subtarget->is64Bit() ? X86::RAX : X86::EAX;
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return DAG.getCopyFromReg(Chain, DL, Reg, getPointerTy());
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}
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assert(false &&
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"TLS not implemented for this target.");
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@ -6280,7 +6280,7 @@ SDValue X86TargetLowering::LowerSINT_TO_FP(SDValue Op,
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}
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SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
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SDValue StackSlot,
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SDValue StackSlot,
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SelectionDAG &DAG) const {
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// Build the FILD
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DebugLoc DL = Op.getDebugLoc();
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@ -6290,15 +6290,15 @@ SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
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Tys = DAG.getVTList(MVT::f64, MVT::Other, MVT::Flag);
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else
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Tys = DAG.getVTList(Op.getValueType(), MVT::Other);
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unsigned ByteSize = SrcVT.getSizeInBits()/8;
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int SSFI = cast<FrameIndexSDNode>(StackSlot)->getIndex();
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MachineMemOperand *MMO =
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DAG.getMachineFunction()
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.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
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MachineMemOperand::MOLoad, ByteSize, ByteSize);
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SDValue Ops[] = { Chain, StackSlot, DAG.getValueType(SrcVT) };
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SDValue Result = DAG.getMemIntrinsicNode(useSSE ? X86ISD::FILD_FLAG :
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X86ISD::FILD, DL,
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@ -6324,7 +6324,7 @@ SDValue X86TargetLowering::BuildFILD(SDValue Op, EVT SrcVT, SDValue Chain,
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DAG.getMachineFunction()
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.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
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MachineMemOperand::MOStore, SSFISize, SSFISize);
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Chain = DAG.getMemIntrinsicNode(X86ISD::FST, DL, Tys,
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Ops, array_lengthof(Ops),
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Op.getValueType(), MMO);
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@ -6516,7 +6516,7 @@ SDValue X86TargetLowering::LowerUINT_TO_FP(SDValue Op,
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DAG.getMachineFunction()
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.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
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MachineMemOperand::MOLoad, 8, 8);
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SDVTList Tys = DAG.getVTList(MVT::f80, MVT::Other);
|
||||
SDValue Ops[] = { Store, StackSlot, DAG.getValueType(MVT::i64) };
|
||||
SDValue Fild = DAG.getMemIntrinsicNode(X86ISD::FILD, dl, Tys, Ops, 3,
|
||||
@ -6582,8 +6582,8 @@ FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
|
||||
int SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
|
||||
SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
||||
|
||||
|
||||
|
||||
|
||||
|
||||
unsigned Opc;
|
||||
switch (DstTy.getSimpleVT().SimpleTy) {
|
||||
default: llvm_unreachable("Invalid FP_TO_SINT to lower!");
|
||||
@ -6604,7 +6604,7 @@ FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
|
||||
SDValue Ops[] = {
|
||||
Chain, StackSlot, DAG.getValueType(TheVT)
|
||||
};
|
||||
|
||||
|
||||
MachineMemOperand *MMO =
|
||||
MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
|
||||
MachineMemOperand::MOLoad, MemSize, MemSize);
|
||||
@ -6614,7 +6614,7 @@ FP_TO_INTHelper(SDValue Op, SelectionDAG &DAG, bool IsSigned) const {
|
||||
SSFI = MF.getFrameInfo()->CreateStackObject(MemSize, MemSize, false);
|
||||
StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
||||
}
|
||||
|
||||
|
||||
MachineMemOperand *MMO =
|
||||
MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
|
||||
MachineMemOperand::MOStore, MemSize, MemSize);
|
||||
@ -7236,7 +7236,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
|
||||
if (Cond.getOpcode() == ISD::AND &&
|
||||
Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
|
||||
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
|
||||
if (C && C->getAPIntValue() == 1)
|
||||
if (C && C->getAPIntValue() == 1)
|
||||
Cond = Cond.getOperand(0);
|
||||
}
|
||||
|
||||
@ -7269,7 +7269,7 @@ SDValue X86TargetLowering::LowerSELECT(SDValue Op, SelectionDAG &DAG) const {
|
||||
|
||||
// We know the result of AND is compared against zero. Try to match
|
||||
// it to BT.
|
||||
if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
|
||||
if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
|
||||
SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
|
||||
if (NewSetCC.getNode()) {
|
||||
CC = NewSetCC.getOperand(0);
|
||||
@ -7343,7 +7343,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
|
||||
if (Cond.getOpcode() == ISD::AND &&
|
||||
Cond.getOperand(0).getOpcode() == X86ISD::SETCC_CARRY) {
|
||||
ConstantSDNode *C = dyn_cast<ConstantSDNode>(Cond.getOperand(1));
|
||||
if (C && C->getAPIntValue() == 1)
|
||||
if (C && C->getAPIntValue() == 1)
|
||||
Cond = Cond.getOperand(0);
|
||||
}
|
||||
|
||||
@ -7444,7 +7444,7 @@ SDValue X86TargetLowering::LowerBRCOND(SDValue Op, SelectionDAG &DAG) const {
|
||||
|
||||
// We know the result of AND is compared against zero. Try to match
|
||||
// it to BT.
|
||||
if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
|
||||
if (Cond.getOpcode() == ISD::AND && Cond.hasOneUse()) {
|
||||
SDValue NewSetCC = LowerToBT(Cond, ISD::SETNE, dl, DAG);
|
||||
if (NewSetCC.getNode()) {
|
||||
CC = NewSetCC.getOperand(0);
|
||||
@ -7579,7 +7579,7 @@ SDValue X86TargetLowering::LowerVACOPY(SDValue Op, SelectionDAG &DAG) const {
|
||||
|
||||
return DAG.getMemcpy(Chain, DL, DstPtr, SrcPtr,
|
||||
DAG.getIntPtrConstant(24), 8, /*isVolatile*/false,
|
||||
false,
|
||||
false,
|
||||
MachinePointerInfo(DstSV), MachinePointerInfo(SrcSV));
|
||||
}
|
||||
|
||||
@ -8117,11 +8117,11 @@ SDValue X86TargetLowering::LowerFLT_ROUNDS_(SDValue Op,
|
||||
int SSFI = MF.getFrameInfo()->CreateStackObject(2, StackAlignment, false);
|
||||
SDValue StackSlot = DAG.getFrameIndex(SSFI, getPointerTy());
|
||||
|
||||
|
||||
|
||||
MachineMemOperand *MMO =
|
||||
MF.getMachineMemOperand(MachinePointerInfo::getFixedStack(SSFI),
|
||||
MachineMemOperand::MOStore, 2, 2);
|
||||
|
||||
|
||||
SDValue Ops[] = { DAG.getEntryNode(), StackSlot };
|
||||
SDValue Chain = DAG.getMemIntrinsicNode(X86ISD::FNSTCW16m, DL,
|
||||
DAG.getVTList(MVT::Other),
|
||||
@ -8278,7 +8278,7 @@ SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
|
||||
Op.getOperand(1), DAG.getConstant(23, MVT::i32));
|
||||
|
||||
ConstantInt *CI = ConstantInt::get(*Context, APInt(32, 0x3f800000U));
|
||||
|
||||
|
||||
std::vector<Constant*> CV(4, CI);
|
||||
Constant *C = ConstantVector::get(CV);
|
||||
SDValue CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
|
||||
@ -8318,13 +8318,13 @@ SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
|
||||
R, M, Op);
|
||||
// a += a
|
||||
Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
|
||||
|
||||
|
||||
C = ConstantVector::get(CVM2);
|
||||
CPIdx = DAG.getConstantPool(C, getPointerTy(), 16);
|
||||
M = DAG.getLoad(VT, dl, DAG.getEntryNode(), CPIdx,
|
||||
MachinePointerInfo::getConstantPool(),
|
||||
false, false, 16);
|
||||
|
||||
|
||||
// r = pblendv(r, psllw(r & (char16)63, 2), a);
|
||||
M = DAG.getNode(ISD::AND, dl, VT, R, M);
|
||||
M = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
|
||||
@ -8335,7 +8335,7 @@ SDValue X86TargetLowering::LowerSHL(SDValue Op, SelectionDAG &DAG) const {
|
||||
R, M, Op);
|
||||
// a += a
|
||||
Op = DAG.getNode(ISD::ADD, dl, VT, Op, Op);
|
||||
|
||||
|
||||
// return pblendv(r, r+r, a);
|
||||
R = DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
|
||||
DAG.getConstant(Intrinsic::x86_sse41_pblendvb, MVT::i32),
|
||||
@ -8415,10 +8415,10 @@ SDValue X86TargetLowering::LowerXALUO(SDValue Op, SelectionDAG &DAG) const {
|
||||
|
||||
SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
|
||||
DebugLoc dl = Op.getDebugLoc();
|
||||
|
||||
|
||||
if (!Subtarget->hasSSE2()) {
|
||||
SDValue Chain = Op.getOperand(0);
|
||||
SDValue Zero = DAG.getConstant(0,
|
||||
SDValue Zero = DAG.getConstant(0,
|
||||
Subtarget->is64Bit() ? MVT::i64 : MVT::i32);
|
||||
SDValue Ops[] = {
|
||||
DAG.getRegister(X86::ESP, MVT::i32), // Base
|
||||
@ -8429,30 +8429,30 @@ SDValue X86TargetLowering::LowerMEMBARRIER(SDValue Op, SelectionDAG &DAG) const{
|
||||
Zero,
|
||||
Chain
|
||||
};
|
||||
SDNode *Res =
|
||||
SDNode *Res =
|
||||
DAG.getMachineNode(X86::OR32mrLocked, dl, MVT::Other, Ops,
|
||||
array_lengthof(Ops));
|
||||
return SDValue(Res, 0);
|
||||
}
|
||||
|
||||
|
||||
unsigned isDev = cast<ConstantSDNode>(Op.getOperand(5))->getZExtValue();
|
||||
if (!isDev)
|
||||
return DAG.getNode(X86ISD::MEMBARRIER, dl, MVT::Other, Op.getOperand(0));
|
||||
|
||||
|
||||
unsigned Op1 = cast<ConstantSDNode>(Op.getOperand(1))->getZExtValue();
|
||||
unsigned Op2 = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
|
||||
unsigned Op3 = cast<ConstantSDNode>(Op.getOperand(3))->getZExtValue();
|
||||
unsigned Op4 = cast<ConstantSDNode>(Op.getOperand(4))->getZExtValue();
|
||||
|
||||
|
||||
// def : Pat<(membarrier (i8 0), (i8 0), (i8 0), (i8 1), (i8 1)), (SFENCE)>;
|
||||
if (!Op1 && !Op2 && !Op3 && Op4)
|
||||
return DAG.getNode(X86ISD::SFENCE, dl, MVT::Other, Op.getOperand(0));
|
||||
|
||||
|
||||
// def : Pat<(membarrier (i8 1), (i8 0), (i8 0), (i8 0), (i8 1)), (LFENCE)>;
|
||||
if (Op1 && !Op2 && !Op3 && !Op4)
|
||||
return DAG.getNode(X86ISD::LFENCE, dl, MVT::Other, Op.getOperand(0));
|
||||
|
||||
// def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
|
||||
|
||||
// def : Pat<(membarrier (i8 imm), (i8 imm), (i8 imm), (i8 imm), (i8 1)),
|
||||
// (MFENCE)>;
|
||||
return DAG.getNode(X86ISD::MFENCE, dl, MVT::Other, Op.getOperand(0));
|
||||
}
|
||||
@ -8512,10 +8512,10 @@ SDValue X86TargetLowering::LowerBIT_CONVERT(SDValue Op,
|
||||
SelectionDAG &DAG) const {
|
||||
EVT SrcVT = Op.getOperand(0).getValueType();
|
||||
EVT DstVT = Op.getValueType();
|
||||
assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
|
||||
assert((Subtarget->is64Bit() && !Subtarget->hasSSE2() &&
|
||||
Subtarget->hasMMX() && !DisableMMX) &&
|
||||
"Unexpected custom BIT_CONVERT");
|
||||
assert((DstVT == MVT::i64 ||
|
||||
assert((DstVT == MVT::i64 ||
|
||||
(DstVT.isVector() && DstVT.getSizeInBits()==64)) &&
|
||||
"Unexpected custom BIT_CONVERT");
|
||||
// i64 <=> MMX conversions are Legal.
|
||||
@ -9575,20 +9575,20 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
|
||||
// our load from the relocation, sticking it in either RDI (x86-64)
|
||||
// or EAX and doing an indirect call. The return value will then
|
||||
// be in the normal return register.
|
||||
const X86InstrInfo *TII
|
||||
const X86InstrInfo *TII
|
||||
= static_cast<const X86InstrInfo*>(getTargetMachine().getInstrInfo());
|
||||
DebugLoc DL = MI->getDebugLoc();
|
||||
MachineFunction *F = BB->getParent();
|
||||
|
||||
assert(Subtarget->isTargetDarwin() && "Darwin only instr emitted?");
|
||||
assert(MI->getOperand(3).isGlobal() && "This should be a global");
|
||||
|
||||
|
||||
if (Subtarget->is64Bit()) {
|
||||
MachineInstrBuilder MIB = BuildMI(*BB, MI, DL,
|
||||
TII->get(X86::MOV64rm), X86::RDI)
|
||||
.addReg(X86::RIP)
|
||||
.addImm(0).addReg(0)
|
||||
.addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
|
||||
.addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
|
||||
MI->getOperand(3).getTargetFlags())
|
||||
.addReg(0);
|
||||
MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL64m));
|
||||
@ -9598,7 +9598,7 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
|
||||
TII->get(X86::MOV32rm), X86::EAX)
|
||||
.addReg(0)
|
||||
.addImm(0).addReg(0)
|
||||
.addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
|
||||
.addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
|
||||
MI->getOperand(3).getTargetFlags())
|
||||
.addReg(0);
|
||||
MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
|
||||
@ -9608,13 +9608,13 @@ X86TargetLowering::EmitLoweredTLSCall(MachineInstr *MI,
|
||||
TII->get(X86::MOV32rm), X86::EAX)
|
||||
.addReg(TII->getGlobalBaseReg(F))
|
||||
.addImm(0).addReg(0)
|
||||
.addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
|
||||
.addGlobalAddress(MI->getOperand(3).getGlobal(), 0,
|
||||
MI->getOperand(3).getTargetFlags())
|
||||
.addReg(0);
|
||||
MIB = BuildMI(*BB, MI, DL, TII->get(X86::CALL32m));
|
||||
addDirectMem(MIB, X86::EAX);
|
||||
}
|
||||
|
||||
|
||||
MI->eraseFromParent(); // The pseudo instruction is gone now.
|
||||
return BB;
|
||||
}
|
||||
@ -9952,7 +9952,7 @@ unsigned X86TargetLowering::ComputeNumSignBitsForTargetNode(SDValue Op,
|
||||
// SETCC_CARRY sets the dest to ~0 for true or 0 for false.
|
||||
if (Op.getOpcode() == X86ISD::SETCC_CARRY)
|
||||
return Op.getValueType().getScalarType().getSizeInBits();
|
||||
|
||||
|
||||
// Fallback case.
|
||||
return 1;
|
||||
}
|
||||
|
||||
Loading…
Reference in New Issue
Block a user