mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-23 02:29:18 +00:00
Some ARM implementaions, e.g. A-series, does return stack prediction. That is,
the processor keeps a return addresses stack (RAS) which stores the address and the instruction execution state of the instruction after a function-call type branch instruction. Calling a "noreturn" function with normal call instructions (e.g. bl) can corrupt RAS and causes 100% return misprediction so LLVM should use a unconditional branch instead. i.e. mov lr, pc b _foo The "mov lr, pc" is issued in order to get proper backtrace. rdar://8979299 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@151623 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -1233,7 +1233,8 @@ public:
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LowerCallTo(SDValue Chain, Type *RetTy, bool RetSExt, bool RetZExt,
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bool isVarArg, bool isInreg, unsigned NumFixedArgs,
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CallingConv::ID CallConv, bool isTailCall,
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bool isReturnValueUsed, SDValue Callee, ArgListTy &Args,
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bool doesNotRet, bool isReturnValueUsed,
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SDValue Callee, ArgListTy &Args,
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SelectionDAG &DAG, DebugLoc dl) const;
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/// LowerCall - This hook must be implemented to lower calls into the
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@ -1245,7 +1246,7 @@ public:
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virtual SDValue
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LowerCall(SDValue /*Chain*/, SDValue /*Callee*/,
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CallingConv::ID /*CallConv*/, bool /*isVarArg*/,
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bool &/*isTailCall*/,
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bool /*doesNotRet*/, bool &/*isTailCall*/,
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const SmallVectorImpl<ISD::OutputArg> &/*Outs*/,
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const SmallVectorImpl<SDValue> &/*OutVals*/,
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const SmallVectorImpl<ISD::InputArg> &/*Ins*/,
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@ -1788,7 +1788,7 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, SDNode *Node,
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std::pair<SDValue, SDValue> CallInfo =
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TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
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0, TLI.getLibcallCallingConv(LC), isTailCall,
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/*isReturnValueUsed=*/true,
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/*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
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Callee, Args, DAG, Node->getDebugLoc());
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if (!CallInfo.second.getNode())
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@ -1821,7 +1821,7 @@ SDValue SelectionDAGLegalize::ExpandLibCall(RTLIB::Libcall LC, EVT RetVT,
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std::pair<SDValue,SDValue> CallInfo =
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TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
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false, 0, TLI.getLibcallCallingConv(LC), false,
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/*isReturnValueUsed=*/true,
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/*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
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Callee, Args, DAG, dl);
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return CallInfo.first;
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@ -1853,7 +1853,7 @@ SelectionDAGLegalize::ExpandChainLibCall(RTLIB::Libcall LC,
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std::pair<SDValue, SDValue> CallInfo =
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TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
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0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
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/*isReturnValueUsed=*/true,
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/*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
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Callee, Args, DAG, Node->getDebugLoc());
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return CallInfo;
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@ -1985,7 +1985,8 @@ SelectionDAGLegalize::ExpandDivRemLibCall(SDNode *Node,
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std::pair<SDValue, SDValue> CallInfo =
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TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
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0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
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/*isReturnValueUsed=*/true, Callee, Args, DAG, dl);
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/*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
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Callee, Args, DAG, dl);
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// Remainder is loaded back from the stack frame.
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SDValue Rem = DAG.getLoad(RetVT, dl, CallInfo.second, FIPtr,
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@ -2563,7 +2564,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
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false, false, false, false, 0, CallingConv::C,
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/*isTailCall=*/false,
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/*isReturnValueUsed=*/true,
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/*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
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DAG.getExternalSymbol("__sync_synchronize",
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TLI.getPointerTy()),
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Args, DAG, dl);
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@ -2640,7 +2641,7 @@ void SelectionDAGLegalize::ExpandNode(SDNode *Node) {
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TLI.LowerCallTo(Node->getOperand(0), Type::getVoidTy(*DAG.getContext()),
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false, false, false, false, 0, CallingConv::C,
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/*isTailCall=*/false,
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/*isReturnValueUsed=*/true,
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/*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
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DAG.getExternalSymbol("abort", TLI.getPointerTy()),
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Args, DAG, dl);
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Results.push_back(CallResult.second);
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@ -2311,8 +2311,10 @@ void DAGTypeLegalizer::ExpandIntRes_XMULO(SDNode *N,
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SDValue Func = DAG.getExternalSymbol(TLI.getLibcallName(LC), PtrVT);
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std::pair<SDValue, SDValue> CallInfo =
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TLI.LowerCallTo(Chain, RetTy, true, false, false, false,
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0, TLI.getLibcallCallingConv(LC), false,
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true, Func, Args, DAG, dl);
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0, TLI.getLibcallCallingConv(LC),
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/*isTailCall=*/false,
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/*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
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Func, Args, DAG, dl);
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SplitInteger(CallInfo.first, Lo, Hi);
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SDValue Temp2 = DAG.getLoad(PtrVT, dl, CallInfo.second, Temp,
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@ -1056,8 +1056,9 @@ SDValue DAGTypeLegalizer::MakeLibCall(RTLIB::Libcall LC, EVT RetVT,
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Type *RetTy = RetVT.getTypeForEVT(*DAG.getContext());
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std::pair<SDValue,SDValue> CallInfo =
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TLI.LowerCallTo(DAG.getEntryNode(), RetTy, isSigned, !isSigned, false,
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false, 0, TLI.getLibcallCallingConv(LC), false,
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/*isReturnValueUsed=*/true,
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false, 0, TLI.getLibcallCallingConv(LC),
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/*isTailCall=*/false,
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/*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
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Callee, Args, DAG, dl);
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return CallInfo.first;
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}
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@ -1088,7 +1089,7 @@ DAGTypeLegalizer::ExpandChainLibCall(RTLIB::Libcall LC,
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std::pair<SDValue, SDValue> CallInfo =
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TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
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0, TLI.getLibcallCallingConv(LC), /*isTailCall=*/false,
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/*isReturnValueUsed=*/true,
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/*doesNotReturn=*/false, /*isReturnValueUsed=*/true,
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Callee, Args, DAG, Node->getDebugLoc());
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return CallInfo;
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@ -3736,8 +3736,9 @@ SDValue SelectionDAG::getMemcpy(SDValue Chain, DebugLoc dl, SDValue Dst,
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std::pair<SDValue,SDValue> CallResult =
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TLI.LowerCallTo(Chain, Type::getVoidTy(*getContext()),
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false, false, false, false, 0,
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TLI.getLibcallCallingConv(RTLIB::MEMCPY), false,
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/*isReturnValueUsed=*/false,
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TLI.getLibcallCallingConv(RTLIB::MEMCPY),
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/*isTailCall=*/false,
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/*doesNotReturn=*/false, /*isReturnValueUsed=*/false,
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getExternalSymbol(TLI.getLibcallName(RTLIB::MEMCPY),
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TLI.getPointerTy()),
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Args, *this, dl);
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@ -3788,8 +3789,9 @@ SDValue SelectionDAG::getMemmove(SDValue Chain, DebugLoc dl, SDValue Dst,
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std::pair<SDValue,SDValue> CallResult =
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TLI.LowerCallTo(Chain, Type::getVoidTy(*getContext()),
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false, false, false, false, 0,
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TLI.getLibcallCallingConv(RTLIB::MEMMOVE), false,
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/*isReturnValueUsed=*/false,
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TLI.getLibcallCallingConv(RTLIB::MEMMOVE),
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/*isTailCall=*/false,
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/*doesNotReturn=*/false, /*isReturnValueUsed=*/false,
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getExternalSymbol(TLI.getLibcallName(RTLIB::MEMMOVE),
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TLI.getPointerTy()),
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Args, *this, dl);
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@ -3848,8 +3850,9 @@ SDValue SelectionDAG::getMemset(SDValue Chain, DebugLoc dl, SDValue Dst,
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std::pair<SDValue,SDValue> CallResult =
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TLI.LowerCallTo(Chain, Type::getVoidTy(*getContext()),
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false, false, false, false, 0,
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TLI.getLibcallCallingConv(RTLIB::MEMSET), false,
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/*isReturnValueUsed=*/false,
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TLI.getLibcallCallingConv(RTLIB::MEMSET),
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/*isTailCall=*/false,
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/*doesNotReturn*/false, /*isReturnValueUsed=*/false,
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getExternalSymbol(TLI.getLibcallName(RTLIB::MEMSET),
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TLI.getPointerTy()),
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Args, *this, dl);
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@ -5081,7 +5081,8 @@ SelectionDAGBuilder::visitIntrinsicCall(const CallInst &I, unsigned Intrinsic) {
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std::pair<SDValue, SDValue> Result =
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TLI.LowerCallTo(getRoot(), I.getType(),
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false, false, false, false, 0, CallingConv::C,
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/*isTailCall=*/false, /*isReturnValueUsed=*/true,
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/*isTailCall=*/false,
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/*doesNotRet=*/false, /*isReturnValueUsed=*/true,
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DAG.getExternalSymbol(TrapFuncName.data(), TLI.getPointerTy()),
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Args, DAG, getCurDebugLoc());
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DAG.setRoot(Result.second);
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@ -5244,6 +5245,7 @@ void SelectionDAGBuilder::LowerCallTo(ImmutableCallSite CS, SDValue Callee,
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CS.paramHasAttr(0, Attribute::InReg), FTy->getNumParams(),
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CS.getCallingConv(),
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isTailCall,
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CS.doesNotReturn(),
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!CS.getInstruction()->use_empty(),
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Callee, Args, DAG, getCurDebugLoc());
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assert((isTailCall || Result.second.getNode()) &&
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@ -6360,7 +6362,7 @@ TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy,
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bool RetSExt, bool RetZExt, bool isVarArg,
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bool isInreg, unsigned NumFixedArgs,
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CallingConv::ID CallConv, bool isTailCall,
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bool isReturnValueUsed,
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bool doesNotRet, bool isReturnValueUsed,
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SDValue Callee,
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ArgListTy &Args, SelectionDAG &DAG,
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DebugLoc dl) const {
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@ -6457,7 +6459,7 @@ TargetLowering::LowerCallTo(SDValue Chain, Type *RetTy,
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}
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SmallVector<SDValue, 4> InVals;
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Chain = LowerCall(Chain, Callee, CallConv, isVarArg, isTailCall,
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Chain = LowerCall(Chain, Callee, CallConv, isVarArg, doesNotRet, isTailCall,
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Outs, OutVals, Ins, dl, DAG, InVals);
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// Verify that the target's LowerCall behaved as expected.
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@ -89,6 +89,11 @@ def FeatureAvoidPartialCPSR : SubtargetFeature<"avoid-partial-cpsr",
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"AvoidCPSRPartialUpdate", "true",
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"Avoid CPSR partial update for OOO execution">;
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// Some processors perform return stack prediction. CodeGen should avoid issue
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// "normal" call instructions to callees which do not return.
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def FeatureHasRAS : SubtargetFeature<"ras", "HasRAS", "true",
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"Has return address stack">;
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/// Some M architectures don't have the DSP extension (v7E-M vs. v7M)
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def FeatureDSPThumb2 : SubtargetFeature<"t2dsp", "Thumb2DSP", "true",
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"Supports v7 DSP instructions in Thumb2">;
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@ -204,13 +209,14 @@ def : Processor<"arm1156t2f-s", ARMV6Itineraries, [HasV6T2Ops, FeatureVFP2,
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// V7a Processors.
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def : Processor<"cortex-a8", CortexA8Itineraries,
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[ProcA8, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2]>;
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FeatureDSPThumb2, FeatureHasRAS]>;
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def : Processor<"cortex-a9", CortexA9Itineraries,
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[ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2]>;
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FeatureDSPThumb2, FeatureHasRAS]>;
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def : Processor<"cortex-a9-mp", CortexA9Itineraries,
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[ProcA9, HasV7Ops, FeatureNEON, FeatureDB,
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FeatureDSPThumb2, FeatureMP]>;
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FeatureDSPThumb2, FeatureMP,
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FeatureHasRAS]>;
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// V7M Processors.
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def : ProcNoItin<"cortex-m3", [HasV7Ops,
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@ -1343,6 +1343,60 @@ void ARMAsmPrinter::EmitInstruction(const MachineInstr *MI) {
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}
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return;
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}
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case ARM::BMOVPCBr9_CALL:
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case ARM::BMOVPCB_CALL: {
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::MOVr);
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TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
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TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
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// Add predicate operands.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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// Add 's' bit operand (always reg0 for this)
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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}
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::Bcc);
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const GlobalValue *GV = MI->getOperand(0).getGlobal();
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MCSymbol *GVSym = Mang->getSymbol(GV);
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const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
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TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
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// Add predicate operands.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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}
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return;
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}
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case ARM::t2BMOVPCBr9_CALL:
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case ARM::t2BMOVPCB_CALL: {
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::tMOVr);
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TmpInst.addOperand(MCOperand::CreateReg(ARM::LR));
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TmpInst.addOperand(MCOperand::CreateReg(ARM::PC));
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// Add predicate operands.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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}
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{
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MCInst TmpInst;
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TmpInst.setOpcode(ARM::t2B);
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const GlobalValue *GV = MI->getOperand(0).getGlobal();
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MCSymbol *GVSym = Mang->getSymbol(GV);
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const MCExpr *GVSymExpr = MCSymbolRefExpr::Create(GVSym, OutContext);
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TmpInst.addOperand(MCOperand::CreateExpr(GVSymExpr));
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// Add predicate operands.
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TmpInst.addOperand(MCOperand::CreateImm(ARMCC::AL));
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TmpInst.addOperand(MCOperand::CreateReg(0));
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OutStreamer.EmitInstruction(TmpInst);
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}
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return;
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}
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case ARM::MOVi16_ga_pcrel:
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case ARM::t2MOVi16_ga_pcrel: {
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MCInst TmpInst;
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@ -1286,7 +1286,7 @@ void ARMTargetLowering::PassF64ArgInRegs(DebugLoc dl, SelectionDAG &DAG,
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SDValue
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ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg,
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bool &isTailCall,
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bool doesNotRet, bool &isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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@ -1582,12 +1582,20 @@ ARMTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
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if (Subtarget->isThumb()) {
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if ((!isDirect || isARMFunc) && !Subtarget->hasV5TOps())
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CallOpc = ARMISD::CALL_NOLINK;
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else if (doesNotRet && !isARMFunc &&
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Subtarget->hasRAS() && !Subtarget->isThumb1Only())
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// "mov lr, pc; b _foo" to avoid confusing the RSP
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CallOpc = ARMISD::CALL_NOLINK;
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else
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CallOpc = isARMFunc ? ARMISD::CALL : ARMISD::tCALL;
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} else {
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CallOpc = (isDirect || Subtarget->hasV5TOps())
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? (isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL)
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: ARMISD::CALL_NOLINK;
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if (!isDirect && !Subtarget->hasV5TOps()) {
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CallOpc = ARMISD::CALL_NOLINK;
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} else if (doesNotRet && Subtarget->hasRAS())
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// "mov lr, pc; b _foo" to avoid confusing the RSP
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CallOpc = ARMISD::CALL_NOLINK;
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else
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CallOpc = isLocalARMFunc ? ARMISD::CALL_PRED : ARMISD::CALL;
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}
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std::vector<SDValue> Ops;
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@ -2080,7 +2088,8 @@ ARMTargetLowering::LowerToTLSGeneralDynamicModel(GlobalAddressSDNode *GA,
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std::pair<SDValue, SDValue> CallResult =
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LowerCallTo(Chain, (Type *) Type::getInt32Ty(*DAG.getContext()),
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false, false, false, false,
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0, CallingConv::C, false, /*isReturnValueUsed=*/true,
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0, CallingConv::C, /*isTailCall=*/false,
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/*doesNotRet=*/false, /*isReturnValueUsed=*/true,
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DAG.getExternalSymbol("__tls_get_addr", PtrVT), Args, DAG, dl);
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return CallResult.first;
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}
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@ -462,7 +462,7 @@ namespace llvm {
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virtual SDValue
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LowerCall(SDValue Chain, SDValue Callee,
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CallingConv::ID CallConv, bool isVarArg,
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bool &isTailCall,
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bool doesNotRet, bool &isTailCall,
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const SmallVectorImpl<ISD::OutputArg> &Outs,
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const SmallVectorImpl<SDValue> &OutVals,
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const SmallVectorImpl<ISD::InputArg> &Ins,
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@ -1951,6 +1951,13 @@ let isCall = 1,
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def BMOVPCRX_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
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8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
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Requires<[IsARM, NoV4T, IsNotIOS]>;
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// mov lr, pc; b if callee is marked noreturn to avoid confusing the
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// return stack predictor.
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def BMOVPCB_CALL : ARMPseudoInst<(outs),
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(ins bl_target:$func, variable_ops),
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8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
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Requires<[IsARM, IsNotIOS]>;
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}
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let isCall = 1,
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@ -1993,6 +2000,12 @@ let isCall = 1,
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def BMOVPCRXr9_CALL : ARMPseudoInst<(outs), (ins tGPR:$func, variable_ops),
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8, IIC_Br, [(ARMcall_nolink tGPR:$func)]>,
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Requires<[IsARM, NoV4T, IsIOS]>;
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// mov lr, pc; b if callee is marked noreturn to avoid confusing the
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// return stack predictor.
|
||||
def BMOVPCBr9_CALL : ARMPseudoInst<(outs),(ins bl_target:$func, variable_ops),
|
||||
8, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
|
||||
Requires<[IsARM, IsIOS]>;
|
||||
}
|
||||
|
||||
let isBranch = 1, isTerminator = 1 in {
|
||||
@ -4897,6 +4910,12 @@ def : ARMPat<(ARMcall texternalsym:$func), (BL texternalsym:$func)>,
|
||||
Requires<[IsARM, IsNotIOS]>;
|
||||
def : ARMPat<(ARMcall texternalsym:$func), (BLr9 texternalsym:$func)>,
|
||||
Requires<[IsARM, IsIOS]>;
|
||||
def : ARMPat<(ARMcall_nolink texternalsym:$func),
|
||||
(BMOVPCB_CALL texternalsym:$func)>,
|
||||
Requires<[IsARM, IsNotIOS]>;
|
||||
def : ARMPat<(ARMcall_nolink texternalsym:$func),
|
||||
(BMOVPCBr9_CALL texternalsym:$func)>,
|
||||
Requires<[IsARM, IsIOS]>;
|
||||
|
||||
// zextload i1 -> zextload i8
|
||||
def : ARMPat<(zextloadi1 addrmode_imm12:$addr), (LDRBi12 addrmode_imm12:$addr)>;
|
||||
|
@ -3277,6 +3277,38 @@ let isCall = 1, isTerminator = 1, isReturn = 1, isBarrier = 1 in {
|
||||
Requires<[IsThumb2, IsIOS]>;
|
||||
}
|
||||
|
||||
let isCall = 1,
|
||||
// On non-IOS platforms R9 is callee-saved.
|
||||
Defs = [LR], Uses = [SP] in {
|
||||
// mov lr, pc; b if callee is marked noreturn to avoid confusing the
|
||||
// return stack predictor.
|
||||
def t2BMOVPCB_CALL : tPseudoInst<(outs),
|
||||
(ins t_bltarget:$func, variable_ops),
|
||||
6, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
|
||||
Requires<[IsThumb, IsNotIOS]>;
|
||||
}
|
||||
|
||||
let isCall = 1,
|
||||
// On IOS R9 is call-clobbered.
|
||||
// R7 is marked as a use to prevent frame-pointer assignments from being
|
||||
// moved above / below calls.
|
||||
Defs = [LR], Uses = [R7, SP] in {
|
||||
// mov lr, pc; b if callee is marked noreturn to avoid confusing the
|
||||
// return stack predictor.
|
||||
def t2BMOVPCBr9_CALL : tPseudoInst<(outs),
|
||||
(ins t_bltarget:$func, variable_ops),
|
||||
6, IIC_Br, [(ARMcall_nolink tglobaladdr:$func)]>,
|
||||
Requires<[IsThumb, IsIOS]>;
|
||||
}
|
||||
|
||||
// Direct calls
|
||||
def : T2Pat<(ARMcall_nolink texternalsym:$func),
|
||||
(t2BMOVPCB_CALL texternalsym:$func)>,
|
||||
Requires<[IsThumb, IsNotIOS]>;
|
||||
def : T2Pat<(ARMcall_nolink texternalsym:$func),
|
||||
(t2BMOVPCBr9_CALL texternalsym:$func)>,
|
||||
Requires<[IsThumb, IsIOS]>;
|
||||
|
||||
// IT block
|
||||
let Defs = [ITSTATE] in
|
||||
def t2IT : Thumb2XI<(outs), (ins it_pred:$cc, it_mask:$mask),
|
||||
|
@ -189,6 +189,7 @@ EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
|
||||
0, // number of fixed arguments
|
||||
TLI.getLibcallCallingConv(RTLIB::MEMSET), // call conv
|
||||
false, // is tail call
|
||||
false, // does not return
|
||||
false, // is return val used
|
||||
DAG.getExternalSymbol(TLI.getLibcallName(RTLIB::MEMSET),
|
||||
TLI.getPointerTy()), // callee
|
||||
|
@ -125,6 +125,10 @@ protected:
|
||||
/// CPSR setting instruction.
|
||||
bool AvoidCPSRPartialUpdate;
|
||||
|
||||
/// HasRAS - Some processors perform return stack prediction. CodeGen should
|
||||
/// avoid issue "normal" call instructions to callees which do not return.
|
||||
bool HasRAS;
|
||||
|
||||
/// HasMPExtension - True if the subtarget supports Multiprocessing
|
||||
/// extension (ARMv7 only).
|
||||
bool HasMPExtension;
|
||||
@ -214,6 +218,7 @@ protected:
|
||||
bool isFPOnlySP() const { return FPOnlySP; }
|
||||
bool prefers32BitThumb() const { return Pref32BitThumb; }
|
||||
bool avoidCPSRPartialUpdate() const { return AvoidCPSRPartialUpdate; }
|
||||
bool hasRAS() const { return HasRAS; }
|
||||
bool hasMPExtension() const { return HasMPExtension; }
|
||||
bool hasThumb2DSP() const { return Thumb2DSP; }
|
||||
|
||||
|
@ -83,8 +83,9 @@ namespace {
|
||||
Op.getNode()->getValueType(0).getTypeForEVT(*DAG.getContext());
|
||||
std::pair<SDValue, SDValue> CallInfo =
|
||||
TLI.LowerCallTo(InChain, RetTy, isSigned, !isSigned, false, false,
|
||||
0, TLI.getLibcallCallingConv(LC), false,
|
||||
/*isReturnValueUsed=*/true,
|
||||
0, TLI.getLibcallCallingConv(LC),
|
||||
/*isTailCall=*/false,
|
||||
/*doesNotRet=*/false, /*isReturnValueUsed=*/true,
|
||||
Callee, Args, DAG, Op.getDebugLoc());
|
||||
|
||||
return CallInfo.first;
|
||||
@ -1274,7 +1275,7 @@ static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) {
|
||||
SDValue
|
||||
SPUTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
bool &isTailCall,
|
||||
bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -162,7 +162,7 @@ namespace llvm {
|
||||
virtual SDValue
|
||||
LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
bool &isTailCall,
|
||||
bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -371,7 +371,7 @@ HexagonTargetLowering::LowerCallResult(SDValue Chain, SDValue InFlag,
|
||||
SDValue
|
||||
HexagonTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
bool &isTailCall,
|
||||
bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -96,7 +96,7 @@ namespace llvm {
|
||||
|
||||
SDValue LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
bool &isTailCall,
|
||||
bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -682,7 +682,7 @@ static bool CC_MBlaze_AssignReg(unsigned &ValNo, MVT &ValVT, MVT &LocVT,
|
||||
/// TODO: isVarArg, isTailCall.
|
||||
SDValue MBlazeTargetLowering::
|
||||
LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
|
||||
bool isVarArg, bool &isTailCall,
|
||||
bool isVarArg, bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -134,7 +134,7 @@ namespace llvm {
|
||||
virtual SDValue
|
||||
LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
bool &isTailCall,
|
||||
bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -268,7 +268,7 @@ MSP430TargetLowering::LowerFormalArguments(SDValue Chain,
|
||||
SDValue
|
||||
MSP430TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
bool &isTailCall,
|
||||
bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -152,8 +152,8 @@ namespace llvm {
|
||||
DebugLoc dl, SelectionDAG &DAG,
|
||||
SmallVectorImpl<SDValue> &InVals) const;
|
||||
virtual SDValue
|
||||
LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
||||
LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
|
||||
bool isVarArg, bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -1586,7 +1586,9 @@ LowerGlobalTLSAddress(SDValue Op, SelectionDAG &DAG) const
|
||||
|
||||
std::pair<SDValue, SDValue> CallResult =
|
||||
LowerCallTo(DAG.getEntryNode(), PtrTy,
|
||||
false, false, false, false, 0, CallingConv::C, false, true,
|
||||
false, false, false, false, 0, CallingConv::C,
|
||||
/*isTailCall=*/false, /*doesNotRet=*/false,
|
||||
/*isReturnValueUsed=*/true,
|
||||
TlsGetAddr, Args, DAG, dl);
|
||||
|
||||
SDValue Ret = CallResult.first;
|
||||
@ -2190,7 +2192,7 @@ PassByValArg64(SDValue& ByValChain, SDValue Chain, DebugLoc dl,
|
||||
SDValue
|
||||
MipsTargetLowering::LowerCall(SDValue InChain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
bool &isTailCall,
|
||||
bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -144,7 +144,7 @@ namespace llvm {
|
||||
virtual SDValue
|
||||
LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
bool &isTailCall,
|
||||
bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -373,7 +373,7 @@ SDValue PTXTargetLowering::
|
||||
SDValue
|
||||
PTXTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
bool &isTailCall,
|
||||
bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -64,9 +64,8 @@ class PTXTargetLowering : public TargetLowering {
|
||||
SelectionDAG &DAG) const;
|
||||
|
||||
virtual SDValue
|
||||
LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
bool &isTailCall,
|
||||
LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
|
||||
bool isVarArg, bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -1427,8 +1427,9 @@ SDValue PPCTargetLowering::LowerINIT_TRAMPOLINE(SDValue Op,
|
||||
// Lower to a call to __trampoline_setup(Trmp, TrampSize, FPtr, ctx_reg)
|
||||
std::pair<SDValue, SDValue> CallResult =
|
||||
LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
|
||||
false, false, false, false, 0, CallingConv::C, false,
|
||||
/*isReturnValueUsed=*/true,
|
||||
false, false, false, false, 0, CallingConv::C,
|
||||
/*isTailCall=*/false,
|
||||
/*doesNotRet=*/false, /*isReturnValueUsed=*/true,
|
||||
DAG.getExternalSymbol("__trampoline_setup", PtrVT),
|
||||
Args, DAG, dl);
|
||||
|
||||
@ -2838,7 +2839,7 @@ PPCTargetLowering::FinishCall(CallingConv::ID CallConv, DebugLoc dl,
|
||||
SDValue
|
||||
PPCTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
bool &isTailCall,
|
||||
bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -437,8 +437,8 @@ namespace llvm {
|
||||
SmallVectorImpl<SDValue> &InVals) const;
|
||||
|
||||
virtual SDValue
|
||||
LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
||||
LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
|
||||
bool isVarArg, bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
@ -472,21 +472,21 @@ namespace llvm {
|
||||
SmallVectorImpl<SDValue> &InVals) const;
|
||||
|
||||
SDValue
|
||||
LowerCall_Darwin(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
|
||||
LowerCall_Darwin(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
|
||||
bool isVarArg, bool isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
DebugLoc dl, SelectionDAG &DAG,
|
||||
SmallVectorImpl<SDValue> &InVals) const;
|
||||
SDValue
|
||||
LowerCall_SVR4(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg, bool isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
DebugLoc dl, SelectionDAG &DAG,
|
||||
SmallVectorImpl<SDValue> &InVals) const;
|
||||
LowerCall_SVR4(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
|
||||
bool isVarArg, bool isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
DebugLoc dl, SelectionDAG &DAG,
|
||||
SmallVectorImpl<SDValue> &InVals) const;
|
||||
};
|
||||
}
|
||||
|
||||
|
@ -347,7 +347,7 @@ SparcTargetLowering::LowerFormalArguments(SDValue Chain,
|
||||
SDValue
|
||||
SparcTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
bool &isTailCall,
|
||||
bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -77,9 +77,8 @@ namespace llvm {
|
||||
SmallVectorImpl<SDValue> &InVals) const;
|
||||
|
||||
virtual SDValue
|
||||
LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
bool &isTailCall,
|
||||
LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
|
||||
bool isVarArg, bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -2119,7 +2119,7 @@ EmitTailCallStoreRetAddr(SelectionDAG & DAG, MachineFunction &MF,
|
||||
SDValue
|
||||
X86TargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
bool &isTailCall,
|
||||
bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -789,8 +789,8 @@ namespace llvm {
|
||||
DebugLoc dl, SelectionDAG &DAG,
|
||||
SmallVectorImpl<SDValue> &InVals) const;
|
||||
virtual SDValue
|
||||
LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg, bool &isTailCall,
|
||||
LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
|
||||
bool isVarArg, bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -65,7 +65,8 @@ X86SelectionDAGInfo::EmitTargetCodeForMemset(SelectionDAG &DAG, DebugLoc dl,
|
||||
std::pair<SDValue,SDValue> CallResult =
|
||||
TLI.LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()),
|
||||
false, false, false, false,
|
||||
0, CallingConv::C, false, /*isReturnValueUsed=*/false,
|
||||
0, CallingConv::C, /*isTailCall=*/false,
|
||||
/*doesNotRet=*/false, /*isReturnValueUsed=*/false,
|
||||
DAG.getExternalSymbol(bzeroEntry, IntPtr), Args,
|
||||
DAG, dl);
|
||||
return CallResult.second;
|
||||
|
@ -487,8 +487,8 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
|
||||
|
||||
std::pair<SDValue, SDValue> CallResult =
|
||||
LowerCallTo(Chain, IntPtrTy, false, false,
|
||||
false, false, 0, CallingConv::C, false,
|
||||
/*isReturnValueUsed=*/true,
|
||||
false, false, 0, CallingConv::C, /*isTailCall=*/false,
|
||||
/*doesNotRet=*/false, /*isReturnValueUsed=*/true,
|
||||
DAG.getExternalSymbol("__misaligned_load", getPointerTy()),
|
||||
Args, DAG, DL);
|
||||
|
||||
@ -549,8 +549,8 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG) const
|
||||
|
||||
std::pair<SDValue, SDValue> CallResult =
|
||||
LowerCallTo(Chain, Type::getVoidTy(*DAG.getContext()), false, false,
|
||||
false, false, 0, CallingConv::C, false,
|
||||
/*isReturnValueUsed=*/true,
|
||||
false, false, 0, CallingConv::C, /*isTailCall=*/false,
|
||||
/*doesNotRet=*/false, /*isReturnValueUsed=*/true,
|
||||
DAG.getExternalSymbol("__misaligned_store", getPointerTy()),
|
||||
Args, DAG, dl);
|
||||
|
||||
@ -875,7 +875,7 @@ LowerINIT_TRAMPOLINE(SDValue Op, SelectionDAG &DAG) const {
|
||||
SDValue
|
||||
XCoreTargetLowering::LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
bool &isTailCall,
|
||||
bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
@ -175,9 +175,8 @@ namespace llvm {
|
||||
SmallVectorImpl<SDValue> &InVals) const;
|
||||
|
||||
virtual SDValue
|
||||
LowerCall(SDValue Chain, SDValue Callee,
|
||||
CallingConv::ID CallConv, bool isVarArg,
|
||||
bool &isTailCall,
|
||||
LowerCall(SDValue Chain, SDValue Callee, CallingConv::ID CallConv,
|
||||
bool isVarArg, bool doesNotRet, bool &isTailCall,
|
||||
const SmallVectorImpl<ISD::OutputArg> &Outs,
|
||||
const SmallVectorImpl<SDValue> &OutVals,
|
||||
const SmallVectorImpl<ISD::InputArg> &Ins,
|
||||
|
30
test/CodeGen/ARM/call-noret.ll
Normal file
30
test/CodeGen/ARM/call-noret.ll
Normal file
@ -0,0 +1,30 @@
|
||||
; RUN: llc < %s -mtriple=armv7-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=ARM
|
||||
; RUN: llc < %s -mtriple=thumbv7-apple-ios -mcpu=cortex-a8 | FileCheck %s -check-prefix=T2
|
||||
; rdar://8979299
|
||||
|
||||
define void @t1() noreturn nounwind ssp {
|
||||
entry:
|
||||
; ARM: t1:
|
||||
; ARM: mov lr, pc
|
||||
; ARM: b _bar
|
||||
|
||||
; T2: t1:
|
||||
; T2: blx _bar
|
||||
tail call void @bar() noreturn nounwind
|
||||
unreachable
|
||||
}
|
||||
|
||||
define void @t2() noreturn nounwind ssp {
|
||||
entry:
|
||||
; ARM: t2:
|
||||
; ARM: mov lr, pc
|
||||
; ARM: b _t1
|
||||
|
||||
; T2: t2:
|
||||
; T2: mov lr, pc
|
||||
; T2: b.w _t1
|
||||
tail call void @t1() noreturn nounwind
|
||||
unreachable
|
||||
}
|
||||
|
||||
declare void @bar() noreturn
|
Loading…
Reference in New Issue
Block a user