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https://github.com/c64scene-ar/llvm-6502.git
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clang-format a bit of code to make the next patch easier to read.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@203203 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Rafael Espindola
parent
49dd5e831b
commit
ec7ab53570
@ -43,22 +43,22 @@ class MCSymbol;
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class MachineOperand {
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public:
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enum MachineOperandType {
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MO_Register, ///< Register operand.
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MO_Immediate, ///< Immediate operand
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MO_CImmediate, ///< Immediate >64bit operand
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MO_FPImmediate, ///< Floating-point immediate operand
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MO_MachineBasicBlock, ///< MachineBasicBlock reference
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MO_FrameIndex, ///< Abstract Stack Frame Index
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MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
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MO_TargetIndex, ///< Target-dependent index+offset operand.
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MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
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MO_ExternalSymbol, ///< Name of external global symbol
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MO_GlobalAddress, ///< Address of a global value
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MO_BlockAddress, ///< Address of a basic block
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MO_RegisterMask, ///< Mask of preserved registers.
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MO_RegisterLiveOut, ///< Mask of live-out registers.
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MO_Metadata, ///< Metadata reference (for debug info)
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MO_MCSymbol ///< MCSymbol reference (for debug/eh info)
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MO_Register, ///< Register operand.
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MO_Immediate, ///< Immediate operand
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MO_CImmediate, ///< Immediate >64bit operand
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MO_FPImmediate, ///< Floating-point immediate operand
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MO_MachineBasicBlock, ///< MachineBasicBlock reference
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MO_FrameIndex, ///< Abstract Stack Frame Index
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MO_ConstantPoolIndex, ///< Address of indexed Constant in Constant Pool
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MO_TargetIndex, ///< Target-dependent index+offset operand.
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MO_JumpTableIndex, ///< Address of indexed Jump Table for switch
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MO_ExternalSymbol, ///< Name of external global symbol
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MO_GlobalAddress, ///< Address of a global value
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MO_BlockAddress, ///< Address of a basic block
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MO_RegisterMask, ///< Mask of preserved registers.
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MO_RegisterLiveOut, ///< Mask of live-out registers.
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MO_Metadata, ///< Metadata reference (for debug info)
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MO_MCSymbol ///< MCSymbol reference (for debug/eh info)
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};
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private:
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@ -150,13 +150,13 @@ private:
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/// Contents union - This contains the payload for the various operand types.
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union {
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MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
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const ConstantFP *CFP; // For MO_FPImmediate.
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const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
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int64_t ImmVal; // For MO_Immediate.
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const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
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const MDNode *MD; // For MO_Metadata.
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MCSymbol *Sym; // For MO_MCSymbol
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MachineBasicBlock *MBB; // For MO_MachineBasicBlock.
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const ConstantFP *CFP; // For MO_FPImmediate.
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const ConstantInt *CI; // For MO_CImmediate. Integers > 64bit.
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int64_t ImmVal; // For MO_Immediate.
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const uint32_t *RegMask; // For MO_RegisterMask and MO_RegisterLiveOut.
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const MDNode *MD; // For MO_Metadata.
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MCSymbol *Sym; // For MO_MCSymbol
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struct { // For MO_Register.
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// Register number is in SmallContents.RegNo.
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@ -22,90 +22,90 @@ namespace llvm {
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/// must be the same as in CodeGenTarget.cpp.
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///
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namespace TargetOpcode {
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enum {
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PHI = 0,
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INLINEASM = 1,
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PROLOG_LABEL = 2,
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EH_LABEL = 3,
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GC_LABEL = 4,
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enum {
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PHI = 0,
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INLINEASM = 1,
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PROLOG_LABEL = 2,
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EH_LABEL = 3,
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GC_LABEL = 4,
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/// KILL - This instruction is a noop that is used only to adjust the
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/// liveness of registers. This can be useful when dealing with
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/// sub-registers.
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KILL = 5,
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/// KILL - This instruction is a noop that is used only to adjust the
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/// liveness of registers. This can be useful when dealing with
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/// sub-registers.
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KILL = 5,
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/// EXTRACT_SUBREG - This instruction takes two operands: a register
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/// that has subregisters, and a subregister index. It returns the
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/// extracted subregister value. This is commonly used to implement
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/// truncation operations on target architectures which support it.
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EXTRACT_SUBREG = 6,
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/// EXTRACT_SUBREG - This instruction takes two operands: a register
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/// that has subregisters, and a subregister index. It returns the
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/// extracted subregister value. This is commonly used to implement
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/// truncation operations on target architectures which support it.
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EXTRACT_SUBREG = 6,
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/// INSERT_SUBREG - This instruction takes three operands: a register that
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/// has subregisters, a register providing an insert value, and a
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/// subregister index. It returns the value of the first register with the
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/// value of the second register inserted. The first register is often
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/// defined by an IMPLICIT_DEF, because it is commonly used to implement
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/// anyext operations on target architectures which support it.
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INSERT_SUBREG = 7,
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/// INSERT_SUBREG - This instruction takes three operands: a register that
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/// has subregisters, a register providing an insert value, and a
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/// subregister index. It returns the value of the first register with the
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/// value of the second register inserted. The first register is often
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/// defined by an IMPLICIT_DEF, because it is commonly used to implement
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/// anyext operations on target architectures which support it.
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INSERT_SUBREG = 7,
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/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
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IMPLICIT_DEF = 8,
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/// IMPLICIT_DEF - This is the MachineInstr-level equivalent of undef.
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IMPLICIT_DEF = 8,
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/// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
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/// the first operand is an immediate integer constant. This constant is
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/// often zero, because it is commonly used to assert that the instruction
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/// defining the register implicitly clears the high bits.
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SUBREG_TO_REG = 9,
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/// SUBREG_TO_REG - This instruction is similar to INSERT_SUBREG except that
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/// the first operand is an immediate integer constant. This constant is
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/// often zero, because it is commonly used to assert that the instruction
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/// defining the register implicitly clears the high bits.
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SUBREG_TO_REG = 9,
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/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
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/// register-to-register copy into a specific register class. This is only
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/// used between instruction selection and MachineInstr creation, before
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/// virtual registers have been created for all the instructions, and it's
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/// only needed in cases where the register classes implied by the
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/// instructions are insufficient. It is emitted as a COPY MachineInstr.
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COPY_TO_REGCLASS = 10,
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/// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
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/// register-to-register copy into a specific register class. This is only
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/// used between instruction selection and MachineInstr creation, before
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/// virtual registers have been created for all the instructions, and it's
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/// only needed in cases where the register classes implied by the
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/// instructions are insufficient. It is emitted as a COPY MachineInstr.
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COPY_TO_REGCLASS = 10,
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/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
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DBG_VALUE = 11,
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/// DBG_VALUE - a mapping of the llvm.dbg.value intrinsic
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DBG_VALUE = 11,
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/// REG_SEQUENCE - This variadic instruction is used to form a register that
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/// represents a consecutive sequence of sub-registers. It's used as a
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/// register coalescing / allocation aid and must be eliminated before code
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/// emission.
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// In SDNode form, the first operand encodes the register class created by
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// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
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// pair. Once it has been lowered to a MachineInstr, the regclass operand
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// is no longer present.
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/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
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/// After register coalescing references of v1024 should be replace with
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/// v1027:3, v1025 with v1027:4, etc.
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REG_SEQUENCE = 12,
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/// REG_SEQUENCE - This variadic instruction is used to form a register that
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/// represents a consecutive sequence of sub-registers. It's used as a
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/// register coalescing / allocation aid and must be eliminated before code
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/// emission.
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// In SDNode form, the first operand encodes the register class created by
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// the REG_SEQUENCE, while each subsequent pair names a vreg + subreg index
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// pair. Once it has been lowered to a MachineInstr, the regclass operand
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// is no longer present.
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/// e.g. v1027 = REG_SEQUENCE v1024, 3, v1025, 4, v1026, 5
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/// After register coalescing references of v1024 should be replace with
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/// v1027:3, v1025 with v1027:4, etc.
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REG_SEQUENCE = 12,
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/// COPY - Target-independent register copy. This instruction can also be
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/// used to copy between subregisters of virtual registers.
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COPY = 13,
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/// COPY - Target-independent register copy. This instruction can also be
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/// used to copy between subregisters of virtual registers.
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COPY = 13,
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/// BUNDLE - This instruction represents an instruction bundle. Instructions
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/// which immediately follow a BUNDLE instruction which are marked with
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/// 'InsideBundle' flag are inside the bundle.
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BUNDLE = 14,
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/// BUNDLE - This instruction represents an instruction bundle. Instructions
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/// which immediately follow a BUNDLE instruction which are marked with
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/// 'InsideBundle' flag are inside the bundle.
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BUNDLE = 14,
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/// Lifetime markers.
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LIFETIME_START = 15,
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LIFETIME_END = 16,
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/// Lifetime markers.
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LIFETIME_START = 15,
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LIFETIME_END = 16,
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/// A Stackmap instruction captures the location of live variables at its
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/// position in the instruction stream. It is followed by a shadow of bytes
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/// that must lie within the function and not contain another stackmap.
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STACKMAP = 17,
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/// A Stackmap instruction captures the location of live variables at its
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/// position in the instruction stream. It is followed by a shadow of bytes
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/// that must lie within the function and not contain another stackmap.
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STACKMAP = 17,
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/// Patchable call instruction - this instruction represents a call to a
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/// constant address, followed by a series of NOPs. It is intended to
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/// support optimizations for dynamic languages (such as javascript) that
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/// rewrite calls to runtimes with more efficient code sequences.
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/// This also implies a stack map.
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PATCHPOINT = 18
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};
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/// Patchable call instruction - this instruction represents a call to a
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/// constant address, followed by a series of NOPs. It is intended to
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/// support optimizations for dynamic languages (such as javascript) that
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/// rewrite calls to runtimes with more efficient code sequences.
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/// This also implies a stack map.
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PATCHPOINT = 18
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};
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} // end namespace TargetOpcode
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} // end namespace llvm
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@ -294,27 +294,11 @@ GetInstByName(const char *Name,
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void CodeGenTarget::ComputeInstrsByEnum() const {
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// The ordering here must match the ordering in TargetOpcodes.h.
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static const char *const FixedInstrs[] = {
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"PHI",
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"INLINEASM",
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"PROLOG_LABEL",
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"EH_LABEL",
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"GC_LABEL",
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"KILL",
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"EXTRACT_SUBREG",
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"INSERT_SUBREG",
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"IMPLICIT_DEF",
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"SUBREG_TO_REG",
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"COPY_TO_REGCLASS",
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"DBG_VALUE",
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"REG_SEQUENCE",
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"COPY",
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"BUNDLE",
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"LIFETIME_START",
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"LIFETIME_END",
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"STACKMAP",
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"PATCHPOINT",
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0
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};
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"PHI", "INLINEASM", "PROLOG_LABEL", "EH_LABEL",
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"GC_LABEL", "KILL", "EXTRACT_SUBREG", "INSERT_SUBREG",
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"IMPLICIT_DEF", "SUBREG_TO_REG", "COPY_TO_REGCLASS", "DBG_VALUE",
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"REG_SEQUENCE", "COPY", "BUNDLE", "LIFETIME_START",
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"LIFETIME_END", "STACKMAP", "PATCHPOINT", 0};
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const DenseMap<const Record*, CodeGenInstruction*> &Insts = getInstructions();
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for (const char *const *p = FixedInstrs; *p; ++p) {
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const CodeGenInstruction *Instr = GetInstByName(*p, Insts, Records);
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