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Fix ARM getInstrLatency logic to work with the current API.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@158161 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -2592,7 +2592,7 @@ ARMBaseInstrInfo::getOperandLatency(const InstrItineraryData *ItinData,
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return 0;
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// Otherwise it takes the instruction latency (generally one).
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int Latency = getInstrLatency(ItinData, DefMI);
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unsigned Latency = getInstrLatency(ItinData, DefMI);
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// For Thumb2 and -Os, prefer scheduling CPSR setting instruction close to
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// its uses. Instructions which are otherwise scheduled between them may
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@ -2991,13 +2991,10 @@ unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
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MI->isRegSequence() || MI->isImplicitDef())
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return 1;
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// Be sure to call getStageLatency for an empty itinerary in case it has a
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// valid MinLatency property.
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if (!ItinData)
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return 1;
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// An instruction scheduler typically runs on unbundled instructions, however
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// other passes may query the latency of a bundled instruction.
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if (MI->isBundle()) {
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int Latency = 0;
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unsigned Latency = 0;
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MachineBasicBlock::const_instr_iterator I = MI;
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MachineBasicBlock::const_instr_iterator E = MI->getParent()->instr_end();
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while (++I != E && I->isInsideBundle()) {
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@ -3008,15 +3005,24 @@ unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
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}
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const MCInstrDesc &MCID = MI->getDesc();
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unsigned Class = MCID.getSchedClass();
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unsigned UOps = ItinData->Itineraries[Class].NumMicroOps;
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if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR)))
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if (PredCost && (MCID.isCall() || MCID.hasImplicitDefOfPhysReg(ARM::CPSR))) {
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// When predicated, CPSR is an additional source operand for CPSR updating
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// instructions, this apparently increases their latencies.
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*PredCost = 1;
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if (UOps)
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return ItinData->getStageLatency(Class);
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return getNumMicroOps(ItinData, MI);
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}
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// Be sure to call getStageLatency for an empty itinerary in case it has a
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// valid MinLatency property.
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if (!ItinData)
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return MI->mayLoad() ? 3 : 1;
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unsigned Class = MCID.getSchedClass();
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// For instructions with variable uops, use uops as latency.
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if (!ItinData->isEmpty() && !ItinData->Itineraries[Class].NumMicroOps) {
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return getNumMicroOps(ItinData, MI);
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}
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// For the common case, fall back on the itinerary's latency.
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return ItinData->getStageLatency(Class);
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}
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int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData,
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