Don't cache the instruction and register info from the TargetMachine, because

the internals of TargetMachine could change.


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183492 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Bill Wendling 2013-06-07 06:30:15 +00:00
parent 637eab6a3b
commit ed8b5b55a4
3 changed files with 5 additions and 6 deletions

View File

@ -29,7 +29,7 @@ using namespace llvm;
MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
: MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
RI(tm, *this) {}
RI(tm) {}
void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
MachineBasicBlock::iterator MI,

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@ -32,9 +32,8 @@
using namespace llvm;
// FIXME: Provide proper call frame setup / destroy opcodes.
MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
const TargetInstrInfo &tii)
: MSP430GenRegisterInfo(MSP430::PCW), TM(tm), TII(tii) {
MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm)
: MSP430GenRegisterInfo(MSP430::PCW), TM(tm) {
StackAlign = TM.getFrameLowering()->getStackAlignment();
}
@ -132,6 +131,7 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
// This is actually "load effective address" of the stack slot
// instruction. We have only two-address instructions, thus we need to
// expand it into mov + add
const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
MI.setDesc(TII.get(MSP430::MOV16rr));
MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);

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@ -27,13 +27,12 @@ class MSP430TargetMachine;
struct MSP430RegisterInfo : public MSP430GenRegisterInfo {
private:
MSP430TargetMachine &TM;
const TargetInstrInfo &TII;
/// StackAlign - Default stack alignment.
///
unsigned StackAlign;
public:
MSP430RegisterInfo(MSP430TargetMachine &tm, const TargetInstrInfo &tii);
MSP430RegisterInfo(MSP430TargetMachine &tm);
/// Code Generation virtual methods...
const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;