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Don't cache the instruction and register info from the TargetMachine, because
the internals of TargetMachine could change. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@183492 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -29,7 +29,7 @@ using namespace llvm;
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MSP430InstrInfo::MSP430InstrInfo(MSP430TargetMachine &tm)
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: MSP430GenInstrInfo(MSP430::ADJCALLSTACKDOWN, MSP430::ADJCALLSTACKUP),
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RI(tm, *this) {}
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RI(tm) {}
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void MSP430InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MI,
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@ -32,9 +32,8 @@
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using namespace llvm;
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// FIXME: Provide proper call frame setup / destroy opcodes.
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MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm,
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const TargetInstrInfo &tii)
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: MSP430GenRegisterInfo(MSP430::PCW), TM(tm), TII(tii) {
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MSP430RegisterInfo::MSP430RegisterInfo(MSP430TargetMachine &tm)
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: MSP430GenRegisterInfo(MSP430::PCW), TM(tm) {
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StackAlign = TM.getFrameLowering()->getStackAlignment();
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}
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@ -132,6 +131,7 @@ MSP430RegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
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// This is actually "load effective address" of the stack slot
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// instruction. We have only two-address instructions, thus we need to
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// expand it into mov + add
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const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
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MI.setDesc(TII.get(MSP430::MOV16rr));
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MI.getOperand(FIOperandNum).ChangeToRegister(BasePtr, false);
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@ -27,13 +27,12 @@ class MSP430TargetMachine;
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struct MSP430RegisterInfo : public MSP430GenRegisterInfo {
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private:
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MSP430TargetMachine &TM;
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const TargetInstrInfo &TII;
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/// StackAlign - Default stack alignment.
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///
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unsigned StackAlign;
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public:
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MSP430RegisterInfo(MSP430TargetMachine &tm, const TargetInstrInfo &tii);
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MSP430RegisterInfo(MSP430TargetMachine &tm);
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/// Code Generation virtual methods...
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const uint16_t *getCalleeSavedRegs(const MachineFunction *MF = 0) const;
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