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Dix the 80-columns and remove unsupported v8i16 type from the list of legal vselect types.
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@139324 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -920,7 +920,6 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
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setOperationAction(ISD::VSELECT, MVT::v2f64, Custom);
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setOperationAction(ISD::VSELECT, MVT::v2i64, Custom);
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setOperationAction(ISD::VSELECT, MVT::v16i8, Custom);
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setOperationAction(ISD::VSELECT, MVT::v8i16, Custom);
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setOperationAction(ISD::VSELECT, MVT::v4i32, Custom);
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setOperationAction(ISD::VSELECT, MVT::v4f32, Custom);
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@ -8703,16 +8702,20 @@ SDValue X86TargetLowering::LowerVSELECT(SDValue Op, SelectionDAG &DAG) const {
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assert(Op2.getValueType().isVector() && "Op2 must be a vector");
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assert(Cond.getValueType().isVector() && "Cond must be a vector");
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assert(Op1.getValueType() == Op2.getValueType() && "Type mismatch");
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switch (Op1.getValueType().getSimpleVT().SimpleTy) {
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EVT VT = Op1.getValueType();
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switch (VT.getSimpleVT().SimpleTy) {
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default: break;
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case MVT::v2i64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
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case MVT::v2f64: return DAG.getNode(X86ISD::BLENDVPD, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
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case MVT::v4i32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
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case MVT::v4f32: return DAG.getNode(X86ISD::BLENDVPS, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
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case MVT::v16i8: return DAG.getNode(X86ISD::PBLENDVB, DL, Op1.getValueType(), Ops, array_lengthof(Ops));
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case MVT::v2i64:
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case MVT::v2f64:
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return DAG.getNode(X86ISD::BLENDVPD, DL, VT, Ops, array_lengthof(Ops));
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case MVT::v4i32:
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case MVT::v4f32:
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return DAG.getNode(X86ISD::BLENDVPS, DL, VT , Ops, array_lengthof(Ops));
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case MVT::v16i8:
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return DAG.getNode(X86ISD::PBLENDVB, DL, VT , Ops, array_lengthof(Ops));
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}
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return SDValue();
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}
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