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https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-22 10:29:35 +00:00
Fixed a few problems with vector shifts
- when transforming a vector shift of a non-immediate scalar shift amount, zero extend the i32 shift amount to i64 since the vector shift reads 64 bits - when transforming i16 vectors to use a vector shift, zero extend i16 shift amount - improve the code quality in some cases when transforming vectors to use a vector shift git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@80935 91177308-0d34-0410-b5e6-96231b3b80d8
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@ -6359,9 +6359,23 @@ X86TargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op, SelectionDAG &DAG) {
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break;
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}
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}
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// The vector shift intrinsics with scalars uses 32b shift amounts but
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// the sse2/mmx shift instructions reads 64 bits. Set the upper 32 bits
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// to be zero.
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SDValue ShOps[4];
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ShOps[0] = ShAmt;
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ShOps[1] = DAG.getConstant(0, MVT::i32);
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if (ShAmtVT == MVT::v4i32) {
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ShOps[2] = DAG.getUNDEF(MVT::i32);
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ShOps[3] = DAG.getUNDEF(MVT::i32);
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ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 4);
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} else {
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ShAmt = DAG.getNode(ISD::BUILD_VECTOR, dl, ShAmtVT, &ShOps[0], 2);
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}
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EVT VT = Op.getValueType();
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ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT,
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DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, ShAmtVT, ShAmt));
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ShAmt = DAG.getNode(ISD::BIT_CONVERT, dl, VT, ShAmt);
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return DAG.getNode(ISD::INTRINSIC_WO_CHAIN, dl, VT,
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DAG.getConstant(NewIntNo, MVT::i32),
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Op.getOperand(1), ShAmt);
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@ -8554,7 +8568,7 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
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SDValue ShAmtOp = N->getOperand(1);
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EVT EltVT = VT.getVectorElementType();
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DebugLoc DL = N->getDebugLoc();
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SDValue BaseShAmt;
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SDValue BaseShAmt = SDValue();
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if (ShAmtOp.getOpcode() == ISD::BUILD_VECTOR) {
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unsigned NumElts = VT.getVectorNumElements();
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unsigned i = 0;
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@ -8573,15 +8587,34 @@ static SDValue PerformShiftCombine(SDNode* N, SelectionDAG &DAG,
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}
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} else if (ShAmtOp.getOpcode() == ISD::VECTOR_SHUFFLE &&
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cast<ShuffleVectorSDNode>(ShAmtOp)->isSplat()) {
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BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
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DAG.getIntPtrConstant(0));
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SDValue InVec = ShAmtOp.getOperand(0);
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if (InVec.getOpcode() == ISD::BUILD_VECTOR) {
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unsigned NumElts = InVec.getValueType().getVectorNumElements();
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unsigned i = 0;
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for (; i != NumElts; ++i) {
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SDValue Arg = InVec.getOperand(i);
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if (Arg.getOpcode() == ISD::UNDEF) continue;
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BaseShAmt = Arg;
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break;
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}
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} else if (InVec.getOpcode() == ISD::INSERT_VECTOR_ELT) {
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if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(InVec.getOperand(2))) {
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unsigned SplatIdx = cast<ShuffleVectorSDNode>(ShAmtOp)->getSplatIndex();
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if (C->getZExtValue() == SplatIdx)
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BaseShAmt = InVec.getOperand(1);
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}
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}
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if (BaseShAmt.getNode() == 0)
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BaseShAmt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, ShAmtOp,
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DAG.getIntPtrConstant(0));
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} else
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return SDValue();
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// The shift amount is an i32.
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if (EltVT.bitsGT(MVT::i32))
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BaseShAmt = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, BaseShAmt);
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else if (EltVT.bitsLT(MVT::i32))
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BaseShAmt = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, BaseShAmt);
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BaseShAmt = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i32, BaseShAmt);
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// The shift amount is identical so we can do a vector shift.
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SDValue ValOp = N->getOperand(0);
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