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Add the PPC64 ldbrx/stdbrx instructions

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These are 64-bit load/store with byte-swap, and available on the P7 and the A2.
Like the similar instructions for 16- and 32-bit words, these are matched in the
target DAG-combine phase against load/store-bswap pairs.

git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@178276 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Hal Finkel
2013-03-28 19:25:55 +00:00
parent ce88835110
commit efdd4673d6
7 changed files with 67 additions and 20 deletions
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30
test/CodeGen/PowerPC/bswap-load-store.ll
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@@ -1,5 +1,6 @@
; RUN: llc < %s -march=ppc32 | FileCheck %s -check-prefix=X32
; RUN: llc < %s -march=ppc64 | FileCheck %s -check-prefix=X64
; RUN: llc < %s -march=ppc64 -mcpu=pwr7 | FileCheck %s -check-prefix=PWR7
define void @STWBRX(i32 %i, i8* %ptr, i32 %off) {
@@ -34,18 +35,47 @@ define i16 @LHBRX(i8* %ptr, i32 %off) {
ret i16 %tmp6
}
define void @STDBRX(i64 %i, i8* %ptr, i64 %off) {
%tmp1 = getelementptr i8* %ptr, i64 %off ; <i8*> [#uses=1]
%tmp1.upgrd.1 = bitcast i8* %tmp1 to i64* ; <i64*> [#uses=1]
%tmp13 = tail call i64 @llvm.bswap.i64( i64 %i ) ; <i64> [#uses=1]
store i64 %tmp13, i64* %tmp1.upgrd.1
ret void
}
define i64 @LDBRX(i8* %ptr, i64 %off) {
%tmp1 = getelementptr i8* %ptr, i64 %off ; <i8*> [#uses=1]
%tmp1.upgrd.2 = bitcast i8* %tmp1 to i64* ; <i64*> [#uses=1]
%tmp = load i64* %tmp1.upgrd.2 ; <i64> [#uses=1]
%tmp14 = tail call i64 @llvm.bswap.i64( i64 %tmp ) ; <i64> [#uses=1]
ret i64 %tmp14
}
declare i32 @llvm.bswap.i32(i32)
declare i16 @llvm.bswap.i16(i16)
declare i64 @llvm.bswap.i64(i64)
; X32: stwbrx
; X32: lwbrx
; X32: sthbrx
; X32: lhbrx
; X32-NOT: ldbrx
; X32-NOT: stdbrx
; X64: stwbrx
; X64: lwbrx
; X64: sthbrx
; X64: lhbrx
; X64-NOT: ldbrx
; X64-NOT: stdbrx
; PWR7: stwbrx
; PWR7: lwbrx
; PWR7: sthbrx
; PWR7: lhbrx
; PWR7: stdbrx
; PWR7: ldbrx