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IMULri* instructions do not require their first two registers operands

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to be the same (IOW they are not two address instructions).


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@11117 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Alkis Evlogimenos 2004-02-04 17:21:04 +00:00
parent 44a6807f4f
commit f0339396c1
3 changed files with 12 additions and 10 deletions
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6
lib/Target/X86/Printer.cpp
View File

@ -666,8 +666,8 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
// ModR/M input. The first two operands should be the same, post register
// allocation. This is for things like: add r32, r/m32
//
// 3 Operands: in this form, we can have 'INST R, R, imm', which is used for
// instructions like the IMULri instructions.
// 3 Operands: in this form, we can have 'INST R1, R2, imm', which is used
// for instructions like the IMULri instructions.
//
// 2 Operands: this is for things like mov that do not read a second input
//
@ -678,7 +678,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
(MI->getOperand(2).isRegister() ||
MI->getOperand(2).isImmediate())))
&& "Bad format for MRMSrcReg!");
if (MI->getNumOperands() == 3 &&
if (MI->getNumOperands() == 3 && !MI->getOperand(2).isImmediate() &&
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
O << "**";

6
lib/Target/X86/X86AsmPrinter.cpp
View File

@ -666,8 +666,8 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
// ModR/M input. The first two operands should be the same, post register
// allocation. This is for things like: add r32, r/m32
//
// 3 Operands: in this form, we can have 'INST R, R, imm', which is used for
// instructions like the IMULri instructions.
// 3 Operands: in this form, we can have 'INST R1, R2, imm', which is used
// for instructions like the IMULri instructions.
//
// 2 Operands: this is for things like mov that do not read a second input
//
@ -678,7 +678,7 @@ void Printer::printMachineInstruction(const MachineInstr *MI) {
(MI->getOperand(2).isRegister() ||
MI->getOperand(2).isImmediate())))
&& "Bad format for MRMSrcReg!");
if (MI->getNumOperands() == 3 &&
if (MI->getNumOperands() == 3 && !MI->getOperand(2).isImmediate() &&
MI->getOperand(0).getReg() != MI->getOperand(1).getReg())
O << "**";

10
lib/Target/X86/X86InstrInfo.td
View File

@ -270,10 +270,12 @@ def SBBrr32 : I2A32<"sbb", 0x19, MRMDestReg>; // R32 -= R32+Carr
def IMULrr16 : I2A16<"imul", 0xAF, MRMSrcReg>, TB, OpSize, Pattern<(set R16, (times R16, R16))>;
def IMULrr32 : I2A32<"imul", 0xAF, MRMSrcReg>, TB , Pattern<(set R32, (times R32, R32))>;
def IMULri16 : I2A16<"imul", 0x69, MRMSrcReg>, OpSize;
def IMULri32 : I2A32<"imul", 0x69, MRMSrcReg>;
def IMULri16b : I2A8<"imul", 0x6B, MRMSrcReg>, OpSize;
def IMULri32b : I2A8<"imul", 0x6B, MRMSrcReg>;
// These are suprisingly enough not two addres instructions!
def IMULri16 : X86Inst<"imul", 0x69, MRMSrcReg, Arg16>, OpSize;
def IMULri32 : X86Inst<"imul", 0x69, MRMSrcReg, Arg32>;
def IMULri16b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8>, OpSize;
def IMULri32b : X86Inst<"imul", 0x6B, MRMSrcReg, Arg8>;
// Logical operators...