mirror of
https://github.com/c64scene-ar/llvm-6502.git
synced 2024-08-17 05:29:24 +00:00
- Added getOpcodeAfterMemoryUnfold(). It doesn't unfold an instruction, but only returns the opcode of the instruction post unfolding.
- Fix some copy+paste bugs. git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@43153 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
parent
58184e6878
commit
f0a0cddbcd
@ -508,7 +508,7 @@ public:
|
||||
const TargetRegisterClass *RC) const = 0;
|
||||
|
||||
virtual void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const = 0;
|
||||
|
||||
@ -518,7 +518,7 @@ public:
|
||||
const TargetRegisterClass *RC) const = 0;
|
||||
|
||||
virtual void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const =0;
|
||||
|
||||
@ -577,6 +577,14 @@ public:
|
||||
return false;
|
||||
}
|
||||
|
||||
/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
|
||||
/// instruction after load / store are unfolded from the specified opcode.
|
||||
/// It returns zero if the specified unfolding is impossible.
|
||||
virtual unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
|
||||
bool UnfoldLoad, bool UnfoldStore) const {
|
||||
return 0;
|
||||
}
|
||||
|
||||
/// targetHandlesStackFrameRounding - Returns true if the target is
|
||||
/// responsible for rounding up the stack frame (probably at emitPrologue
|
||||
/// time).
|
||||
|
@ -183,7 +183,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
}
|
||||
|
||||
void ARMRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||
unsigned Opc = 0;
|
||||
@ -239,7 +239,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
}
|
||||
|
||||
void ARMRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||
unsigned Opc = 0;
|
||||
|
@ -52,7 +52,7 @@ public:
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||
|
||||
@ -62,7 +62,7 @@ public:
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||
|
||||
|
@ -83,7 +83,7 @@ AlphaRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
}
|
||||
|
||||
void AlphaRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||
unsigned Opc = 0;
|
||||
@ -128,7 +128,7 @@ AlphaRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
}
|
||||
|
||||
void AlphaRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||
unsigned Opc = 0;
|
||||
|
@ -34,7 +34,7 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||
|
||||
@ -44,7 +44,7 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||
|
||||
|
@ -61,7 +61,7 @@ void IA64RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
}
|
||||
|
||||
void IA64RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||
unsigned Opc = 0;
|
||||
@ -113,7 +113,7 @@ void IA64RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
}
|
||||
|
||||
void IA64RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||
unsigned Opc = 0;
|
||||
|
@ -35,7 +35,7 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||
|
||||
@ -45,7 +45,7 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||
|
||||
|
@ -96,7 +96,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
}
|
||||
|
||||
void MipsRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||
if (RC != Mips::CPURegsRegisterClass)
|
||||
@ -128,7 +128,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
}
|
||||
|
||||
void MipsRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||
if (RC != Mips::CPURegsRegisterClass)
|
||||
|
@ -38,7 +38,7 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||
|
||||
@ -48,7 +48,7 @@ struct MipsRegisterInfo : public MipsGenRegisterInfo {
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||
|
||||
|
@ -182,7 +182,7 @@ PPCRegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
}
|
||||
|
||||
void PPCRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||
if (Addr[0].isFrameIndex()) {
|
||||
@ -291,7 +291,7 @@ PPCRegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
}
|
||||
|
||||
void PPCRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||
if (Addr[0].isFrameIndex()) {
|
||||
|
@ -41,7 +41,7 @@ public:
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||
|
||||
@ -51,7 +51,7 @@ public:
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||
|
||||
|
@ -49,7 +49,7 @@ storeRegToStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
}
|
||||
|
||||
void SparcRegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||
unsigned Opc = 0;
|
||||
@ -91,7 +91,7 @@ loadRegFromStackSlot(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
|
||||
}
|
||||
|
||||
void SparcRegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||
unsigned Opc = 0;
|
||||
|
@ -36,7 +36,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||
|
||||
@ -46,7 +46,7 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||
|
||||
|
@ -806,7 +806,7 @@ void X86RegisterInfo::storeRegToStackSlot(MachineBasicBlock &MBB,
|
||||
}
|
||||
|
||||
void X86RegisterInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||
unsigned Opc = getStoreRegOpcode(RC);
|
||||
@ -862,7 +862,7 @@ void X86RegisterInfo::loadRegFromStackSlot(MachineBasicBlock &MBB,
|
||||
}
|
||||
|
||||
void X86RegisterInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const {
|
||||
unsigned Opc = getLoadRegOpcode(RC);
|
||||
@ -1273,6 +1273,20 @@ X86RegisterInfo::unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
|
||||
return true;
|
||||
}
|
||||
|
||||
unsigned X86RegisterInfo::getOpcodeAfterMemoryUnfold(unsigned Opc,
|
||||
bool UnfoldLoad, bool UnfoldStore) const {
|
||||
DenseMap<unsigned*, std::pair<unsigned,unsigned> >::iterator I =
|
||||
MemOp2RegOpTable.find((unsigned*)Opc);
|
||||
if (I == MemOp2RegOpTable.end())
|
||||
return 0;
|
||||
bool HasLoad = I->second.second & (1 << 4);
|
||||
bool HasStore = I->second.second & (1 << 5);
|
||||
if (UnfoldLoad && !HasLoad)
|
||||
return 0;
|
||||
if (UnfoldStore && !HasStore)
|
||||
return 0;
|
||||
return I->second.first;
|
||||
}
|
||||
|
||||
const unsigned *
|
||||
X86RegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
|
||||
|
@ -89,7 +89,7 @@ public:
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
void storeRegToAddr(MachineFunction &MF, unsigned SrcReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||
|
||||
@ -99,7 +99,7 @@ public:
|
||||
const TargetRegisterClass *RC) const;
|
||||
|
||||
void loadRegFromAddr(MachineFunction &MF, unsigned DestReg,
|
||||
SmallVectorImpl<MachineOperand> Addr,
|
||||
SmallVectorImpl<MachineOperand> &Addr,
|
||||
const TargetRegisterClass *RC,
|
||||
SmallVectorImpl<MachineInstr*> &NewMIs) const;
|
||||
|
||||
@ -142,6 +142,12 @@ public:
|
||||
bool unfoldMemoryOperand(SelectionDAG &DAG, SDNode *N,
|
||||
SmallVectorImpl<SDNode*> &NewNodes) const;
|
||||
|
||||
/// getOpcodeAfterMemoryUnfold - Returns the opcode of the would be new
|
||||
/// instruction after load / store are unfolded from the specified opcode.
|
||||
/// It returns zero if the specified unfolding is impossible.
|
||||
unsigned getOpcodeAfterMemoryUnfold(unsigned Opc,
|
||||
bool UnfoldLoad, bool UnfoldStore) const;
|
||||
|
||||
/// getCalleeSavedRegs - Return a null-terminated list of all of the
|
||||
/// callee-save registers on this target.
|
||||
const unsigned *getCalleeSavedRegs(const MachineFunction* MF = 0) const;
|
||||
|
Loading…
Reference in New Issue
Block a user