6502/llvm-6502
1
0
Fork 0
mirror of https://github.com/c64scene-ar/llvm-6502.git synced 2024-09-29 13:54:57 +00:00
Code Issues Projects Releases Wiki Activity

Add and-not (bic) patterns. Based heavily on patch by Brian Lucas!

Browse Source 
git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@86471 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Anton Korobeynikov 2009-11-08 15:33:12 +00:00
parent 830fe7bc2d
commit f0b47b7f6d
7 changed files with 85 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

32
lib/Target/MSP430/MSP430InstrInfo.td
View File

@ -462,7 +462,6 @@ def AND16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
(implicit SRW)]>;
}
let isCommutable = 1 in { // X = OR Y, Z == X = OR Z, Y
def OR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
"bis.b\t{$src2, $dst}",
@ -519,6 +518,37 @@ def OR16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
(i16 (load addr:$src))), addr:$dst)]>;
}
// bic does not modify condition codes
def BIC8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
"bic.b\t{$src2, $dst}",
[(set GR8:$dst, (and GR8:$src1, (not GR8:$src2)))]>;
def BIC16rr : Pseudo<(outs GR16:$dst), (ins GR16:$src1, GR16:$src2),
"bic.w\t{$src2, $dst}",
[(set GR16:$dst, (and GR16:$src1, (not GR16:$src2)))]>;
def BIC8rm : Pseudo<(outs GR8:$dst), (ins GR8:$src1, memsrc:$src2),
"bic.b\t{$src2, $dst}",
[(set GR8:$dst, (and GR8:$src1, (not (i8 (load addr:$src2)))))]>;
def BIC16rm : Pseudo<(outs GR16:$dst), (ins GR16:$src1, memsrc:$src2),
"bic.w\t{$src2, $dst}",
[(set GR16:$dst, (and GR16:$src1, (not (i16 (load addr:$src2)))))]>;
let isTwoAddress = 0 in {
def BIC8mr : Pseudo<(outs), (ins memdst:$dst, GR8:$src),
"bic.b\t{$src, $dst}",
[(store (and (load addr:$dst), (not GR8:$src)), addr:$dst)]>;
def BIC16mr : Pseudo<(outs), (ins memdst:$dst, GR16:$src),
"bic.w\t{$src, $dst}",
[(store (and (load addr:$dst), (not GR16:$src)), addr:$dst)]>;
def BIC8mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
"bic.b\t{$src, $dst}",
[(store (and (load addr:$dst), (not (i8 (load addr:$src)))), addr:$dst)]>;
def BIC16mm : Pseudo<(outs), (ins memdst:$dst, memsrc:$src),
"bic.w\t{$src, $dst}",
[(store (and (load addr:$dst), (not (i16 (load addr:$src)))), addr:$dst)]>;
}
let isCommutable = 1 in { // X = XOR Y, Z == X = XOR Z, Y
def XOR8rr : Pseudo<(outs GR8:$dst), (ins GR8:$src1, GR8:$src2),
"xor.b\t{$src2, $dst}",

10
test/CodeGen/MSP430/Inst16mr.ll
View File

@ -37,6 +37,16 @@ define void @bis(i16 %a) nounwind {
ret void
}
define void @bic(i16 zeroext %m) nounwind {
; CHECK: bic:
; CHECK: bic.w r15, &foo
%1 = xor i16 %m, -1
%2 = load i16* @foo
%3 = and i16 %2, %1
store i16 %3, i16* @foo
ret void
}
define void @xor(i16 %a) nounwind {
; CHECK: xor:
; CHECK: xor.w r15, &foo

10
test/CodeGen/MSP430/Inst16rm.ll
View File

@ -19,7 +19,6 @@ define i16 @and(i16 %a) nounwind {
ret i16 %2
}
define i16 @bis(i16 %a) nounwind {
; CHECK: bis:
; CHECK: bis.w &foo, r15
@ -28,6 +27,15 @@ define i16 @bis(i16 %a) nounwind {
ret i16 %2
}
define i16 @bic(i16 %a) nounwind {
; CHECK: bic:
; CHECK: bic.w &foo, r15
%1 = load i16* @foo
%2 = xor i16 %1, -1
%3 = and i16 %a, %2
ret i16 %3
}
define i16 @xor(i16 %a) nounwind {
; CHECK: xor:
; CHECK: xor.w &foo, r15

8
test/CodeGen/MSP430/Inst16rr.ll
View File

@ -29,6 +29,14 @@ define i16 @bis(i16 %a, i16 %b) nounwind {
ret i16 %1
}
define i16 @bic(i16 %a, i16 %b) nounwind {
; CHECK: bic:
; CHECK: bic.w r14, r15
%1 = xor i16 %b, -1
%2 = and i16 %a, %1
ret i16 %2
}
define i16 @xor(i16 %a, i16 %b) nounwind {
; CHECK: xor:
; CHECK: xor.w r14, r15

10
test/CodeGen/MSP430/Inst8mr.ll
View File

@ -37,6 +37,16 @@ define void @bis(i8 %a) nounwind {
ret void
}
define void @bic(i8 zeroext %m) nounwind {
; CHECK: bic:
; CHECK: bic.b r15, &foo
%1 = xor i8 %m, -1
%2 = load i8* @foo
%3 = and i8 %2, %1
store i8 %3, i8* @foo
ret void
}
define void @xor(i8 %a) nounwind {
; CHECK: xor:
; CHECK: xor.b r15, &foo

10
test/CodeGen/MSP430/Inst8rm.ll
View File

@ -19,7 +19,6 @@ define i8 @and(i8 %a) nounwind {
ret i8 %2
}
define i8 @bis(i8 %a) nounwind {
; CHECK: bis:
; CHECK: bis.b &foo, r15
@ -28,6 +27,15 @@ define i8 @bis(i8 %a) nounwind {
ret i8 %2
}
define i8 @bic(i8 %a) nounwind {
; CHECK: bic:
; CHECK: bic.b &foo, r15
%1 = load i8* @foo
%2 = xor i8 %1, -1
%3 = and i8 %a, %2
ret i8 %3
}
define i8 @xor(i8 %a) nounwind {
; CHECK: xor:
; CHECK: xor.b &foo, r15

8
test/CodeGen/MSP430/Inst8rr.ll
View File

@ -29,6 +29,14 @@ define i8 @bis(i8 %a, i8 %b) nounwind {
ret i8 %1
}
define i8 @bic(i8 %a, i8 %b) nounwind {
; CHECK: bic:
; CHECK: bic.b r14, r15
%1 = xor i8 %b, -1
%2 = and i8 %a, %1
ret i8 %2
}
define i8 @xor(i8 %a, i8 %b) nounwind {
; CHECK: xor:
; CHECK: xor.w r14, r15