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Expand insert/extract of a <4 x i32> with a variable index.

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git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@62281 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Mon P Wang 2009-01-15 21:10:20 +00:00
parent bb46f52027
commit f0fcdd8e26
2 changed files with 25 additions and 2 deletions
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12
lib/Target/X86/X86ISelLowering.cpp
View File

@ -766,12 +766,12 @@ X86TargetLowering::X86TargetLowering(X86TargetMachine &TM)
// information.
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v16i8, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v8i16, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Legal);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4i32, Custom);
setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v16i8, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v8i16, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Legal);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4i32, Custom);
setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
if (Subtarget->is64Bit()) {
@ -4248,6 +4248,10 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT_SSE4(SDValue Op,
DAG.getNode(ISD::BIT_CONVERT, MVT::v4i32, Op.getOperand(0)),
Op.getOperand(1));
return DAG.getNode(ISD::BIT_CONVERT, MVT::f32, Extract);
} else if (VT == MVT::i32) {
// ExtractPS works with constant index.
if (isa<ConstantSDNode>(Op.getOperand(1)))
return Op;
}
return SDValue();
}
@ -4362,6 +4366,10 @@ X86TargetLowering::LowerINSERT_VECTOR_ELT_SSE4(SDValue Op, SelectionDAG &DAG){
// combine either bitwise AND or insert of float 0.0 to set these bits.
N2 = DAG.getIntPtrConstant(cast<ConstantSDNode>(N2)->getZExtValue() << 4);
return DAG.getNode(X86ISD::INSERTPS, VT, N0, N1, N2);
} else if (EVT == MVT::i32) {
// InsertPS works with constant index.
if (isa<ConstantSDNode>(N2))
return Op;
}
return SDValue();
}

15
test/CodeGen/X86/vec_insert-8.ll Normal file
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@ -0,0 +1,15 @@
; RUN: llvm-as < %s | llc -march=x86 -mattr=+sse41 -o %t -f
; tests variable insert and extract of a 4 x i32
define <4 x i32> @var_insert(<4 x i32> %x, i32 %val, i32 %idx) nounwind {
entry:
%tmp3 = insertelement <4 x i32> %x, i32 %val, i32 %idx ; <<4 x i32>> [#uses=1]
ret <4 x i32> %tmp3
}
define i32 @var_extract(<4 x i32> %x, i32 %idx) nounwind {
entry:
%tmp3 = extractelement <4 x i32> %x, i32 %idx ; <<i32>> [#uses=1]
ret i32 %tmp3
}