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Sanity check MSRi for invalid mask values and reject it as invalid.

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rdar://problem/9246844


git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@129050 91177308-0d34-0410-b5e6-96231b3b80d8
This commit is contained in:
Johnny Chen 2011-04-07 01:37:34 +00:00
parent 0e382192c1
commit f16f4e09ec
2 changed files with 17 additions and 0 deletions
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5
lib/Target/ARM/Disassembler/ARMDisassemblerCore.cpp
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@ -836,6 +836,11 @@ static bool DisassembleBrFrm(MCInst &MI, unsigned Opcode, uint32_t insn,
// MSRi take a mask, followed by one so_imm operand. The mask contains the
// R Bit in bit 4, and the special register fields in bits 3-0.
if (Opcode == ARM::MSRi) {
// A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate)
// The hints instructions have more specific encodings, so if mask == 0,
// we should reject this as an invalid instruction.
if (slice(insn, 19, 16) == 0)
return false;
MI.addOperand(MCOperand::CreateImm(slice(insn, 22, 22) << 4 /* R Bit */ |
slice(insn, 19, 16) /* Special Reg */ ));
// SOImm is 4-bit rotate amount in bits 11-8 with 8-bit imm in bits 7-0.

12
test/MC/Disassembler/ARM/invalid-MSRi-arm.txt Normal file
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@ -0,0 +1,12 @@
# RUN: llvm-mc --disassemble %s -triple=arm-apple-darwin9 |& grep {invalid instruction encoding}
# Opcode=206 Name=MSRi Format=ARM_FORMAT_BRFRM(2)
# 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
# -------------------------------------------------------------------------------------------------
# | 0: 0: 0: 0| 0: 0: 1: 1| 0: 0: 1: 0| 0: 0: 0: 0| 1: 1: 1: 1| 0: 0: 0: 1| 1: 0: 1: 0| 0: 1: 1: 1|
# -------------------------------------------------------------------------------------------------
#
# A5.2.11 MSR (immediate), and hints & B6.1.6 MSR (immediate)
# The hints instructions have more specific encodings, so if mask == 0,
# we should reject this as an invalid instruction.
0xa7 0xf1 0x20 0x3